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| DATA SHEET MOS INTEGRATED CIRCUIT PD30121 VR4121 64-/32-BIT MICROPROCESSOR TM The PD30121 (VR4121) is one of NEC's VR SeriesTM RISC (Reduced Instruction Set Computer) microprocessors and is a high-performance 64-/32-bit microprocessor employing the MIPS TM RISC architecture. The VR4121 uses the high-performance, super power-saving VR4120TM as the CPU core, and has many peripheral functions such as a DMA controller, software modem interface, serial interface, keyboard interface, IrDA interface, touch panel interface, real-time clock, A/D converter, and D/A converter. Configured with these functions, the VR4121 is suitable for high-speed battery-driven portable information systems. The external memory bus width can be selected from 32 bits and 16 bits, realizing high-speed data transfer. Detailed function descriptions are provided in the following user's manual. Be sure to read it before designing. * VR4121 User's Manual (U13569E) DESCRIPTION FEATURES * Employs 64-bit MIPS architecture * Conforms to MIPS III instruction set (deleting FPU, LL, LLD, SC, and SCD instructions) * Optimized 6-stage pipeline * Supports MIPS16 instruction set * Supports high-speed product-sum operation instructions * Supports four types of operating modes, enabling more effective power-consumption management * Internal maximum operating frequency: 131/168 MHz * On-chip clock generator * Address space physical: 32 bits virtual: 40 bits Integrates 32 double entry TLBs * High-capacity instruction/data separated cache memories Instruction: 16 Kbytes Data: 8 Kbytes * Memory controller (ROM, EDO-type DRAM, synchronous DRAM (SDRAM), synchronous ROM (SROM), and flash memory supported) * Keyboard interface and touch panel interface * 4-channel DMA controller * Serial interface (NS16550 compatible) * IrDA interface for infrared communication * Software modem interface * A/D and D/A converters to support digital voice I/O * Supports ISA bus subset * Power supply voltage: VDD2 = 2.5 V (internal), VDD3 = 3.3 V (external) (131 MHz model) * Package: 224-pin fine-pitch FBGA APPLICATIONS * Battery-driven portable information systems * Embedded controllers, etc. ORDERING INFORMATION Part Number Package 224-pin plastic FBGA (16 x 16) 224-pin plastic FBGA (16 x 16) Internal Maximum Operating Frequency 131 MHz 168 MHz PD30121F1-131-GA1 PD30121F1-168-GA1 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14691EJ1V0DS00 (1st edition) Date Published June 2000 N CP(K) Printed in Japan (c) 2000 PD30121 PIN CONFIGURATION * 224-pin plastic FBGA (16 x 16) PD30121F1-131-GA1 PD30121F1-168-GA1 Bottom view Top view 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VUTRPNMLKJHGFEDCBA ABCDEFGHJKLMNPRTUV Index mark 2 Data Sheet U14691EJ1V0DS00 PD30121 Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 Power Supply 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Pin Name VDD3 SHB# BUSCLK HLDACK# IOCHRDY MEMW# ADD23 VDD3 ADD18 ADD15 ADD8 ADD7 VDD2 DCD#/GPIO15 TXD/CLKSEL2 IRDOUT# IRING VDD3 DATA1 IOR# IOW# LEDOUT# FIRCLK HLDRQ# ZWS# ADD24 ADD21 ADD12 ADD6 GND2 DSR# IRDIN FIRDIN#/SEL BATTINH/BATTINT# OFFHOOK MUTE DATA2 DATA0 SMODE2 CKE GND3 IOCS16# MEMR# ADD22 ADD20 ADD17 ADD13 ADD5 RXD DTR#/CLKSEL0 Pin No. C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 E1 E2 E3 E4 E15 E16 E17 E18 F1 F2 F3 F4 F15 F16 F17 F18 G1 G2 G3 G4 G15 G16 G17 G18 H1 H2 H3 H4 Power Supply 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 3.3 V 3.3 V Pin Name RTS#/CLKSEL1 GND3 ILCSENSE AFERST# DATA5 DATA3 DATA6 GND3 MEMCS16# ADD25/SCLK GND3 ADD19 ADD16 ADD14 VDD3 GND3 ADD4 CTS# GND3 GND3 SDI SDO DATA9 DATA4 DATA7 DATA10 OPD# HSPSCLK FS HC0 DATA13 DATA8 DATA11 DATA14 KPORT3 HSPMCLK TELCON KPORT1 VDD2 DATA12 DATA15 GND3 KPORT7 KPORT2 KPORT0 KPORT5 DATA16/GPIO16 GND2 DATA18/GPIO18 VDD3 Pin No. H15 H16 H17 H18 J1 J2 J3 J4 J15 J16 J17 J18 K1 K2 K3 K4 K15 K16 K17 K18 L1 L2 L3 L4 L15 L16 L17 L18 M1 M2 M3 M4 M15 M16 M17 M18 N1 N2 N3 N4 N15 N16 N17 N18 P1 P2 P3 P4 P15 P16 Power Supply 3.3 V 3.3 V 3.3 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 2.5 V 2.5 V Pin Name GND3 KPORT6 KPORT4 VDD2 DATA20/GPIO20 DATA17/GPlO17 DATA22/GPlO22 DATA19/GPIO19 KSCAN9/GPIO41 VDD3 GND2 KSCAN11/GPIO43 DATA23/GPIO23 DATA26/GPIO26 DATA25/GPIO25 DATA21/GPIO21 KSCAN7/GPIO39 KSCAN10/GPIO42 KSCAN5/GPIO37 KSCAN8/GPIO40 DATA27/GPIO27 DATA31/GPIO31 DATA29/GPIO29 DATA24/GPIO24 KSCAN3/GPIO35 KSCAN6/GPIO38 KSCAN0/GPIO32 KSCAN4/GPIO36 DATA30/GPIO30 VDD3 GND3 DATA28/GPIO28 KSCAN2/GPIO34 MIPS16EN GND3 KSCAN1/GPIO33 VDD2 ADD3 ADD10 GND2 GND3 VDD3 VDDP GND3 ADD9 ADD0 ADD2 ADD11 VDD2 (VDDPD) GNDP Remark # indicates active low. Data Sheet U14691EJ1V0DS00 3 PD30121 Pin No. P17 P18 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 T1 T2 T3 T4 T5 Power Supply 3.3 V 2.5 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Pin Name CLKX2 GND2 (GNDPD) ADD1 POWER GND3 GND3 AUDIOIN DVDD MRAS2#/ULCAS# MRAS1# ROMCS1# RSTOUT GND3 SMODE1/GPIO49 DDIN/GPIO45 GPIO12 GND3 CVDD RTCX2 CLKX1 POWERON RSTSW# GND3 PIUVDD ADIN0 Pin No. T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 Power Supply 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Pin Name AVDD LCAS# ROMCS2# RD# WR# DBUS32/GPIO48 DDOUT/GPIO44 GPIO11 GPIO8 GND3 GND3 GPIO0 RTCX1 MPOWER RTCRST# AGND TPX1 TPY0 ADIN1 DGND UCAS# ROMCS3# LDCRDY DRTS#/GPIO46 GPIO13 Pin No. U13 U14 U15 U16 U17 U18 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 Power Supply 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Pin Name GPIO9 SYSDIR/GPIO6 SCAS#/GPIO5 GPIO1 GPIO2 CGND VDD3 PIUGND TPX0 TPY1 ADIN2 AUDIOOUT MRAS3#/UUCAS# MRAS0# ROMCS0# VDD3 LCDCS# DCTS#/GPIO47 GPIO14 GPIO10 SPOWER/GPIO7 SRAS#/GPIO4 GPIO3 VDD3 Remark # indicates active low. 4 Data Sheet U14691EJ1V0DS00 PD30121 PIN IDENTIFICATION ADD (0:25): ADIN (0:2): AFERST#: AGND: AUDIOIN: AUDIOOUT: AVDD: BATTINH: BATTINT#: BUSCLK: CGND: CKE: CLKSEL (0:2): CLKX1: CLKX2: CTS#: CVDD: DATA (0:31): DBUS32: DCD#: DCTS#: DDIN: DDOUT: DGND: DRTS#: DSR#: DTR#: DVDD: FIRCLK: FIRDIN#: FS: GND2, GND3: GNDP, GNDPD: GPIO (0:49): HC0: HLDACK#: HLDRQ#: HSPMCLK: HSPSCLK: ILCSENSE: IOCHRDY: IOCS16#: IOR#: IOW#: IRDIN: IRDOUT#: IRING: KPORT (0:7): KSCAN (0:11): LCAS#: Address Bus General Purpose Input for A/D AFE Reset GND for A/D Audio Input Audio Output VDD for A/D Battery Inhibit Battery Interrupt Request System Bus Clock GND for Oscillator Clock Enable Clock Select Clock X1 Clock X2 Clear to Send VDD for Oscillator Data Bus Data Bus 32 Data Carrier Detect Debug Serial Clear to Send Debug Serial Data Input Debug Serial Data Output GND for D/A Debug Serial Request to Send Data Set Ready Data Terminal Ready VDD for D/A FIR Clock FIR Data Input Frame Synchronization Ground Ground for PLL General Purpose I/O Hardware Control 0 Hold Acknowledge Hold Request HSP Codec Master Clock HSP Codec Serial Clock Input Loop Current Sensing I/O Channel Ready I/O Chip Select 16 I/O Read I/O Write IrDA Data Input IrDA Data Output Input Ring Key Code Data Input Key Scan Line Lower Column Address Strobe LCDCS#: LCDRDY: LEDOUT#: MEMCS16#: MEMR#: MEMW#: MIPS16EN: MPOWER: MRAS(0:3)#: MUTE: OFFHOOK: OPD#: PIUGND: PIUVDD: POWER: POWERON: RD#: ROMCS(0:3)#: RSTOUT: RSTSW#: RTCRST#: RTCX1: RTCX2: RTS#: RxD: SCAS#: SCLK: SDI: SDO: SEL: SHB#: SMODE (1:2): SPOWER: SRAS#: SYSDIR: TELCON: TPX (0:1): TPY (0:1): TxD: UCAS#: ULCAS#: UUCAS#: VDD2, VDD3: VDDP, VDDPD: WR#: ZWS#: LCD Chip Select LCD Ready LED Output Memory Chip Select 16 Memory Read Memory Write MIPS16 Enable Main Power DRAM Row Address Strobe Mute Off Hook Output Power Down GND for Touch Panel Interface VDD for Touch Panel Interface Power Switch Power On State Read ROM Chip Select System Bus Reset Output Reset Switch Real-time Clock Reset Real-time Clock X1 Real-time Clock X2 Request to Send Receive Data Column Address Strobe for SDRAM/SROM SDRAM/SROM Clock HSP Serial Data Input HSP Serial Data Output IrDA Module Select System Hi-Byte Enable SDRAM Mode SDRAM Power Control Row Address Strobe for SDRAM/SROM System Bus Buffer Direction Telephone Control Touch Panel X I/O Touch Panel Y I/O Transmit Data Upper Column Address Strobe Lower Byte of Upper Column Address Strobe Upper Byte of Upper Column Address Strobe Power Supply Voltage VDD for PLL Write Zero Wait State Remark # indicates active low. Data Sheet U14691EJ1V0DS00 5 PD30121 INTERNAL BLOCK DIAGRAM AND EXAMPLE OF CONNECTION OF EXTERNAL BLOCKS 32.768 kHz 18.432 MHz CODEC AFE OSB LCD module PD16666 OSB PLL GIU HSP KIU RTC LED DSU PD16661 LCD panel 480 x 240 PC card VR4120 CPU core 131/168 MHz PCMCIA /buffer AIU ICU D/A PMU PIU CMU A/D DCU Touch panel ROM/SROM/flash memory EDO DRAM/ SDRAM BCU DMAAU VR4121 SIU FIR RS-232C driver IR driver 48 MHz CPU CORE INTERNAL BLOCK DIAGRAM Virtual address bus Internal data bus Control (o) Control (i) Address/data (o) Address/data (i) Bus interface Data cache (8 Kbytes) Instruction cache (16 Kbytes) CP0 CPU TLB Clock generator Internal clock 6 Data Sheet U14691EJ1V0DS00 PD30121 CONTENTS 1. PIN FUNCTIONS.................................................................................................................................. 8 1.1 1.2 1.3 1.4 Pin Functions .............................................................................................................................................8 Pin Status in Specific Status...................................................................................................................17 Recommended Connection and I/O Circuit Types................................................................................21 Pin I/O Circuits .........................................................................................................................................24 2. 3. 4. ELECTRICAL SPECIFICATIONS...................................................................................................... 25 PACKAGE DRAWING ....................................................................................................................... 71 RECOMMENDED SOLERING CONDITIONS .................................................................................. 72 Data Sheet U14691EJ1V0DS00 7 PD30121 1. PIN FUNCTIONS Remark # indicates active low. 1.1 Pin Functions (1) System bus interface signals (1/3) Signal ADD25/SCLK I/O O Function This function differs depending on how the SMODE (1:2) signal is set. 8 Data Sheet U14691EJ1V0DS00 PD30121 (2/3) Signal ULCAS#/ MRAS2# I/O O Function This function differs depending on how the DBUS32 signal is set and type of memory being accessed. SHB# IOR# IOW# MEMR# MEMW# ZWS# O O O O O I Data Sheet U14691EJ1V0DS00 9 PD30121 (3/3) Signal RSTOUT MEMCS16# I/O O I Function This is the system bus reset signal. It is active when the VR4121 resets the system bus controller (during bus timeout, manipulation of BCUCNTREG1 register, and power-down mode). This is a dynamic bus sizing request signal. Set this signal as active when system bus memory accesses data in 16-bit width. This signal is invalid when 32-bit width is selected using LCD/high-speed system bus. This is a dynamic bus sizing request signal. Set this signal as active when system bus I/O accesses data in 16-bit width. This signal is invalid when 32-bit width is selected using LCD/high-speed system bus. This is the system bus ready signal. Set this signal as active when the system bus controller is ready to be accessed by the VR4121. This is a hold request signal for the system bus and DRAM bus that is sent from an external bus master. This is a hold acknowledge signal for the system bus and DRAM bus that is sent to an external bus master. This function differs depending on the type of memory being accessed. IOCS16# I IOCHRDY HLDRQ# HLDACK# SRAS#/GPIO4 I I O I/O (2) Clock interface signals Signal RTCX1 RTCX2 CLKX1 CLKX2 FIRCLK I/O I O I O I Function This is the 32.768-kHz oscillator's input pin. It is connected to one side of a crystal resonator. This is the 32.768-kHz oscillator's output pin. It is connected to one side of a crystal resonator. This is the 18.432-MHz oscillator's input pin. It is connected to one side of a crystal resonator. This is the 18.432-MHz oscillator's output pin. It is connected to one side of a crystal resonator. This is the 48-MHz clock input pin. Fix this at high level when FIR is not used. 10 Data Sheet U14691EJ1V0DS00 PD30121 (3) Battery monitor interface signals Signal BATTINH/ BATTINT# I/O I Function This function differs depending on how the MPOWER signal is set. (4) Initialization interface signals Signal MPOWER POWERON POWER RSTSW# RTCRST# I/O O O I I I Function This signal indicates the VR4121 is operating. This signal is inactive during Hibernate mode. This signal indicates the VR4121 is ready to operate. It becomes active when a power-on factor is detected and becomes inactive when the BATTINH/BATTINT# signal check operation is completed. This is a VR4121 activation signal. This is a VR4121 reset signal. This signal resets RTC. When power is first supplied to a device, the external agent must assert the signal at this pin for about 2 s. Data Sheet U14691EJ1V0DS00 11 PD30121 (5) RS-232C interface signals Signal RxD CTS# I/O I I Function This is a receive data signal. It is used when the RS-232C controller sends serial data to the VR4121. This is a transmit enable signal. Assert this signal when the RS-232C controller is ready to receive transmission of serial data. This is a carrier detection signal. Assert this signal when valid serial data is being received. It is also used when detecting a power-on factor for the VR4121. When this pin is not used for DCD# signal, this pin can be used as an interrupt detection function for the GIU unit. This is the data set ready signal. Assert this signal when the RS-232C controller is ready to receive/transmit serial data between the controller and the VR4121. This function differs depending on the operating status. DCD#/ GPIO15 I DSR# I TxD/ CLKSEL2, RTS#/ CLKSEL1, DTR#/ CLKSEL0 I/O CLKSEL (2:0) signal CPU core operation frequency (PClock) SDRAM/SROM operation frequency (VTClock) BUSCLK signal frequency (When TClock output) RFU 28.1 MHz 29.5 MHz 32.8 MHz 29.5 MHz 32.8 MHz 30.2 MHz 26.2 MHz BUSCLK signal requency (When 1/4 of TClock) Interrupt control clock frequency (MasterOut) MIN. 111 Note 1 Note 2 Note 2 MAX. RFU 56.2 MHz 59.0 MHz 65.5 MHz 59.0 MHz 65.5 MHz 60.5 MHz 52.4 MHz RFU 168.5 MHz 147.5 MHz 131.1 MHz 118.0 MHz 98.3 MHz 90.7 MHz 78.6 MHz RFU 28.1 MHz 29.5 MHz 32.8 MHz 29.5 MHz 32.8 MHz 30.2 MHz 26.2 MHz RFU 7.0 MHz 7.4 MHz 8.2 MHz 7.4 MHz 8.2 MHz 7.6 MHz 6.6 MHz RFU 7.0 MHz 7.4 MHz 8.2 MHz 7.4 MHz 8.2 MHz 7.6 MHz 6.6 MHz 110 101 100 011 010 001 000 Notes 1. Do not set CLKSEL (2:0) = 111. 2. The settings CLKSEL (2:0) = 110 and 101 are only guaranteed for the 168 MHz model. Do not apply these settings to the 131 MHz model. 12 Data Sheet U14691EJ1V0DS00 PD30121 (6) IrDA interface signals Signal IRDIN I/O I Function This is an IrDA serial data input signal. It is used when the VR4121 sends serial data to the IrDA controller, for both FIR and SIR. If the IrDA controller used is an HP product, however, this signal should be used for only SIR. This function differs according to the IrDA controller used. FIRDIN#/SEL I/O (7) Debug serial interface signals Signal DDOUT/ GPIO44 I/O O Function This is the debug serial data output signal. It is used when the VR4121 sends serial data to an external debug serial controller. When this pin is not used for the DDOUT signal, it can be used as a general-purpose output port. This is the debug serial data input signal. It is used when an external debug serial data controller sends serial data to the VR4121. When this pin is not used for the DDIN signal, it can be used as a general-purpose output port. This is a transmission request signal. The VR4121 asserts this signal before sending serial data. When this pin is not used for the DRTS# signal, it can be used as a general-purpose output port. This is a transmit acknowledge signal. The VR4121 asserts this signal when it is ready to receive transmitted serial data. When this pin is not used for the DCTS# signal, it can be used as a general-purpose output port. DDIN/ GPIO45 I/O DRTS#/ GPIO46 DCTS#/ GPIO47 O I/O (8) Keyboard interface signals Signal KPORT (0:7) KSCAN (0:11)/ GPIO (32:43) I/O I O Function This is a keyboard scan data input signal. It is used to scan for pressed keys on the keyboard. These signal are used as keyboard scan data output signals and a general-purpose output port. The scan line is set as active when scanning for pressed keys on the keyboard. Signals that are not used for KSCAN signals can be used as a general-purpose output port. (9) Audio interface signals Signal AUDIOIN AUDIOOUT I/O I O This pin is the audio input signal. This is an audio output signal. Analog signals that have been converted via the on-chip 10-bit D/A converter are output. Function Data Sheet U14691EJ1V0DS00 13 PD30121 (10) Touch panel/general purpose A/D interface signals Signal TPX (0:1) I/O I/O Function This is an I/O signal that is used for the touch panel. It uses the voltage applied to the X coordinate and the voltage input to the Y coordinate to detect which coordinates on the touch panel are being pressed. This is an I/O signal that is used for the touch panel. It uses the voltage applied to the Y coordinate and the voltage input to the X coordinate to detect which coordinates on the touch panel are being pressed. This is a general-purpose A/D input signal. TPY (0:1) I/O ADIN (0:2) I (11) General-purpose I/O Signals Signal GPIO (0:3) GPIO4/SRAS# GPIO5/SCAS# GPIO6/SYSDIR GPIO7/SPOWER GPIO8 GPIO (9:12) GPIO (13:14) GPIO (16:31)/DATA (16:31) GPIO (32:43)/KSCAN (0:11) GPIO44/DDOUT GPIO45/DDIN GPIO46/DRTS# GPIO47/DCTS# GPIO48/DBUS32 GPIO49/SMODE1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I/O O I/O I/O I/O Function These are maskable power-on factors. After start-up, they are used as ordinary generalpurpose I/O ports. See (1) System bus interface signals. See (1) System bus interface signals. See (1) System bus interface signals. See (1) System bus interface signals. These are general-purpose I/O ports. These are maskable power-on factors. After start-up, they are used as ordinary generalpurpose I/O ports. These are general-purpose I/O ports. See (1) System bus interface signals. See (8) Keyboard interface signals. See (7) Debug serial interface signals. See (7) Debug serial interface signals. See (7) Debug serial interface signals. See (7) Debug serial interface signals. See (14) Initial setting signals. See (14) Initial setting signals. (12) HSP MODEM interface signals Signal IRING ILCSENSE OFFHOOK MUTE AFERST# SDI FS SDO HSPSCLK TELCON HC0 HSPMCLK OPD# I/O I I O O O I I O I O O O O Function RING signal detect signal. This pin becomes active when the RING signal is detected. Handset detect signal On-hook relay control signal Modem speaker mute control signal CODEC reset signal Serial input signal from CODEC Frame synchronization signal from CODEC Serial output signal to CODEC Operation clock input of modem interface block for CODEC Handset relay control signal CODEC control signal Clock output to CODEC Use this pin for controlling power of CODEC and DAA. This signal is set as active when the power supply of CODEC and DAA is ON. 14 Data Sheet U14691EJ1V0DS00 PD30121 (13) LED interface signal Signal LEDOUT# I/O O This is an output signal for lighting LEDs. Function (14) Initial setting signals Signal Name DBUS32/ GPIO48 I/O I/O Function The function differs depending on the operating status. SMODE1/ GPIO49 I/O SMODE2 I 00 MIPS16EN I This pin enables the use of MIPS16 instructions. This signal is sampled at 1RTC clock cycle after the RTCRST# signal changes from low level to high level. 1: Enables the use of MIPS16 instructions. 0: Disables the use of MIPS16 instructions. Data Sheet U14691EJ1V0DS00 15 PD30121 (15) Dedicated VDD and GND signals Signal Name VDDP GNDP VDDPD GNDPD CVDD CGND DVDD Power-Supply System 2.5 V 2.5 V 2.5 V 2.5 V 3.3 V 3.3 V 3.3 V Function Dedicated VDD for the PLL analog unit Dedicated GND for the PLL analog unit Dedicated VDD for the PLL digital unit. Its function is identical to VDD2. Dedicated GND for the PLL digital unit. Its function is identical to GND2. Dedicated VDD for the oscillator Dedicated GND for the oscillator Dedicated VDD for the D/A converter. The voltage applied to this pin becomes the maximum of the analog output of AUDIOOUT signal. Dedicated GND for D/A converter. The voltage applied to this pin becomes the minimum of the analog output of AUDIOOUT signal. Dedicated VDD for the A/D converter. The voltage applied to this pin becomes the maximum voltage that can be detected by the A/D interface signals (8 lines). Dedicated GND for the A/D converter. The voltage applied to this pin becomes the minimum voltage that can be detected by the A/D interface signals (8 lines). Dedicated VDD for touch-sensitive panel interface Dedicated GND for touch-sensitive panel interface Normal 2.5-V system VDD Normal 2.5-V system GND Normal 3.3-V system VDD Normal 3.3-V system GND DGND 3.3 V AVDD 3.3 V AGND 3.3 V PIUVDD PIUGND VDD2 GND2 VDD3 GND3 3.3 V 3.3 V 2.5 V 2.5 V 3.3 V 3.3 V Caution The VR4121 has two types of power supplies. There are no restrictions as to the sequence in which these power supplies are applied. However, do not apply one type of power for more than one second while the other power supply is not applied. 16 Data Sheet U14691EJ1V0DS00 PD30121 1.2 Pin Status in Specific Status (1/4) Pin Name After Reset by the RTC Reset 0 0 0 0/ Hi-Z Hi-Z Hi-Z Hi-Z - Hi-Z Hi-Z Note 4 Note 4 Hi-Z 0 0 0 After Reset by the Deadman's Switch or RSTSW# Signal Note 1 0 0 0/ Hi-Z 1 1 1 - Note 3 1 Note 5 Note 5 1 Note 7 Note 7 0 In the Suspend Mode Note 2 Note 2 Note 2 Note 2 1 1 1 - Note 3 1 Note 6 Note 6 1 0 0 Note 2 In the Hibernate Mode or Shut Down by the HAL Timer 0 0 0 0/ Hi-Z Hi-Z Hi-Z Hi-Z - Note 3 Hi-Z 0 0 1 0 0 0 During a Bus Hold Hi-Z Hi-Z Hi-Z Hi-Z/ Note 2 1 Hi-Z Hi-Z - Note 3 1 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Note 8 ADD25/SCLK ADD (0:24) DATA (0:15) DATA (16:31)/ GPIO (16:31) LCDCS# RD# WR# LCDRDY ROMCS (2:3)# ROMCS (0:1)# UUCAS#/MRAS3# ULCAS#/MRAS2# MRAS (0:1)# UCAS# LCAS# BUSCLK Notes 1. This differs depending on the setting of the SCLK bit in the SDRAMMODEREG register. When SCLK bit has a value of "1": outputs clock. When SCLK bit has a value of "0": low level is output. 2. Maintains the state of the previous Full-speed Mode. 3. When used as the chip select for the ROM or extended ROM, this is the same as ROMCS (0:1)# pins. When used as the RAS for the extended DRAM, this is the same as MRAS (0:1)# pins. 4. When DBUS32 signal = 1, this becomes the high impedance state. When DBUS32 signal = 0, the high level is output. 5. When DBUS32 signal = 1: See Note 7 below. When DBUS32 signal = 0: high level is output. 6. When DBUS32 signal = 1: low level is output. When DBUS32 signal = 0: high level is output. 7. Reset by the RSTSW# signal: The pin outputs a low level. (Self refresh) Reset by the Deadman's switch: The pin outputs a high level. 8. Bus hold from the Suspend Mode: The state of the previous Full-speed Mode is maintained. Bus hold from Full-speed Mode or Standby Mode: Outputs clocks. Remark 0: low level, 1: high level, Hi-Z: high impedance Data Sheet U14691EJ1V0DS00 17 PD30121 (2/4) Pin Name After Reset by the RTC Reset Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z - Hi-Z - - - - Hi-Z 0 - - - - - - 0 0 - - - - Hi-Z Hi-Z Note 4 Note 4 After Reset by the Deadman's Switch or RSTSW# Signal 1 1 1 1 1 - 1 - - - - 1 Note 2 - - - - - - 1 0 - - - - 1 1 - - 1 - - 0 Hi-Z In the Suspend Mode 1 1 1 1 1 - 0 - - - - Note 1 Note 3 - - - - - - 1 0 - - - - 1 1 - - 1 - - 0 Note 3 In the Hibernate Mode or Shut Down by the HAL Timer Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z - Hi-Z - - - - Hi-Z Note 3 - - - - - - 0 0 - - - - 1 1 - - 1 - - 0 Hi-Z During a Bus Hold Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z - Note 1 - - - - Note 1 Hi-Z - - - - - - 1 0 - - - - Note 1 Note 1 - - Note 1 - - Note 1 Note 3 SHB# IOR# IOW# MEMR# MEMW# ZWS# RSTOUT IOCS16# MEMCS16# IOCHRDY HLDRQ# HLDACK# CKE RTCX1 RTCX2 CLKX1 CLKX2 FIRCLK BATTINH/ BATTINT# MPOWER POWERON POWER RSTSW# RTCRST# RxD TxD/CLKSEL2 RTS#/CLKSEL1 CTS# DCD#/GPIO15 DTR#/CLKSEL0 DSR# IRDIN IRDOUT# FIRDIN#/SEL - - Hi-Z Note 4 - - 0 Hi-Z Notes 1. 2. Normal operation proceeds. This differs depending on the setting of the SCLK bit in the SDRAMMODEREG register. When SCLK bit has a value of "1": outputs clock. When SCLK bit has a value of "0": low level is output. 3. 4. Maintains the state of the previous Full-speed Mode. Specify the input data level using a high-resistance pull up or pull down resistor. Remark 0: low level, 1: high level, Hi-Z: high impedance 18 Data Sheet U14691EJ1V0DS00 PD30121 (3/4) Pin Name After Reset by the RTC Reset -/ Hi-Z 1/ 1 1/ 1 -/ Hi-Z - / Hi-Z/ Hi-Z 0 1 Hi-Z - - Hi-Z Hi-Z Hi-Z 0/ Hi-Z 0/ Hi-Z Hi-Z After Reset by the Deadman's Switch or RSTSW# Signal -/ Note 2 1/ Note 2 1/ Note 2 -/ Note 2 - Hi-Z/ Note 2 0 1 Hi-Z - - Hi-Z Note 5/ Hi-Z Note 5/ Hi-Z 0/ Hi-Z 1/ Hi-Z Hi-Z In the Suspend Mode -/ Note 2 1/ Note 2 1/ Note 2 -/ Note 2 - Note 2/ Note 2 Note 2 Note 2 Note 2 - - Note 2 0/ Note 2 0/ Note 2 0/ Note 2 1/ Note 2 Note 2 In the Hibernate Mode or Shut Down by the HAL Timer -/ Note 2 1/ Note 2 1/ Note 2 -/ Note 2 - Hi-Z/ Note 2 0 1 Hi-Z - - Hi-Z Note 4 During a Bus Hold -/ Note 2 1/ Note 2 1/ Note 2 -/ Note 2 - Note 3 Note 3 Note 3 Note 3 - - Note 3 Hi-Z/ Note 3 Hi-Z/ Note 3 Hi-Z/ Note 3 1/ Note 3 Note 3 DDIN / GPIO45 DDOUT / GPIO44 DRTS# / GPIO46 DCTS# / GPIO47 KPORT (0:7) KSCAN (0:11) Note 1 Note 1 Note 1 Note 1 Note 1 GPIO (32:43) AUDIOOUT TPX (0:1) TPY (0:1) ADIN (0:2) AUDIOIN GPIO (0:3) SRAS#/ GPIO4 SCAS#/ GPIO5 SYSDIR/ GPIO6 SPOWER/ GPIO7 GPIO (8:14) 0/ Hi-Z 0/ Hi-Z 0/ Hi-Z 1/ Hi-Z Hi-Z Note 4 Notes 1. Software can switch the function pin and the output port. 2. The state of the previous Full-speed Mode is maintained. 3. Normal operation proceeds. 4. During hibernate mode, the pull-up/pull-down setting is retained. 5. When reset by RSTSW# signal: low level output (self refresh) When reset by deadman's switch: high level output Remark 0: low level, 1: high level, Hi-Z: high impedance Data Sheet U14691EJ1V0DS00 19 PD30121 (4/4) Pin Name After Reset by the RTC Reset - - Hi-Z Hi-Z 0 - - 0 - Hi-Z 0 0 0 1 Hi-Z/ Hi-Z Hi-Z Hi-Z/ Note 5 Hi-Z - After Reset by the Deadman's Switch or RSTSW# Signal - - Hi-Z Hi-Z 0 - - 0 - Hi-Z 0 0 0 Note 3 Hi-Z/ Note 2 Hi-Z Hi-Z/ Note 2 - In the Suspend Mode - - Note 2 Note 2 Note 2 - - Note 2 - Note 2 Note 2 Note 2 Note 2 Note 3 Note 2/ Note 2 Hi-Z Note 2/ Note 2 - In the Hibernate Mode or Shut Down by the HAL Timer - - Hi-Z Hi-Z 0 - - 0 - Hi-Z 0 0 0 Note 3 Hi-Z/ Note 2 Hi-Z Hi-Z/ Note 2 - During a Bus Hold - - Note 2 Note 2 Note 2 - - Note 2 - Note 2 Note 2 Note 2 Note 2 Note 3 Note 2/ Note 2 Hi-Z Note 2/ Note 2 - IRING ILCSENSE OFFHOOK MUTE Note 1 Note 1 AFERST# SDI FS SDO Note 1 HSPSCLK TELCON HC0 Note 1 Note 1 HSPMCLK OPD# Note 1 LEDOUT# DBUS32/ Note 4 GPIO48 MIPS16EN SMODE1/ Note 4 GPIO49 SMODE2 Notes 1. When initializing, always set BSC bit to 1 in the HSPINT register (0x0C00 0020). 2. The state of the previous Full-speed Mode is maintained. 3. Normal operation proceeds. 4. After the RTC reset is released, this functions as an output port. 5. Specify the input data level using a high-resistance pull up or pull down resistor. Remark 0: low level, 1: high level, Hi-Z: high impedance 20 Data Sheet U14691EJ1V0DS00 PD30121 1.3 Recommended Connection and I/O Circuit Types (1/3) Pin Name Internal Processing Slew rate buffer Slew rate buffer - - Slew rate buffer Slew rate buffer Slew rate buffer - Slew rate buffer Slew rate buffer Slew rate buffer Slew rate buffer Slew rate buffer Slew rate buffer Slew rate buffer Slew rate buffer Slew rate buffer Slew rate buffer Slew rate buffer Slew rate buffer Slew rate buffer Note 5 Slew rate buffer Note 5 Note 5 Note 5 External Processing - - - Note 1 - Note 2 Note 2 Note 3 Note 4 - Note 2 Note 2 Note 2 Note 2 Note 2 - Note 2 Note 2 Note 2 Note 2 Note 2 Note 3 Pull up Note 3 Note 3 Note 3 Drive Capability 120 pF 120 pF 40 pF 40 pF 40 pF 120 pF 120 pF - 40 pF 40 pF 120 pF 120 pF 40 pF 120 pF 120 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF - 40 pF - - - I/O Circuit Type A A A A A A A A A A A A A A A A A A A A A A A A A A Recommended Connection of Unused Pins - - - Connect to VDD or GND via resistor Leave open Leave open Leave open Connect to GND Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Connect to VDD Leave open Connect to VDD Connect to VDD Connect to GND ADD25/SCLK ADD (0:24) DATA (0:15) DATA (16:31)/ GPIO (16:31) LCDCS# RD# WR# LCDRDY ROMCS (2:3)# ROMCS (0:1)# UUCAS#/MRAS3# ULCAS#/MRAS2# MRAS (0:1)# UCAS# LCAS# BUSCLK SHB# IOR# IOW# MEMR# MEMW# ZWS# RSTOUT IOCS16# MEMCS16# IOCHRDY Notes 1. Pins DATA (16:31)/GPIO (16:31) in the VR4121 function as GPIO (16:31) signals when using the 16-bit data bus. When using these pins as GPIO (16:31) signals, pull them up or pull down so as not to input an intermediate-level signal. 2. When the bus hold function is used, external pull-up is recommended for the VR4121. 3. Do not input an intermediate-level signal. 4. When used as the RAS signal of extended DRAM, external pull-up is recommended for the VR4121. 5. When the MPOWER pin outputs the low-level, intermediate-level input is enabled. Remarks 1. No specification (-) in the External Processing column indicates that the external processing is unnecessary. 2. No specification (-) in the Recommended Connection of Unused Pins column indicates that the pin is always connected. Data Sheet U14691EJ1V0DS00 21 PD30121 (2/3) Pin Name Internal Processing Note Slew rate buffer - - - - - - Schmitt input - - Schmitt input Schmitt input Schmitt input - - - - Schmitt input - - - - - - - - - External Processing Pull up - - Resonator Resonator Resonator Resonator Resonator - - - - - - - Pull up/ Pull down Pull up/ Pull down - Pull up Pull up/ Pull down - Pull up - Pull up/ Pull down - - - - Drive Capability - 40 pF 120 pF - - - - - - 40 pF 40 pF - - - - 40 pF 40 pF - - 40 pF - - 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF I/O Circuit Type A A A - - - - A B A A B B B A A A A B A A A A A A A A A Recommended Connection of Unused Pins Directly connect to VDD Leave open Leave open - Leave open - Leave open Directly connect to VDD Directly connect to VDD Leave open Leave open - - - Connect to GND - - Connect to VDD Connect to VDD or GND - Connect to VDD Connect to VDD or GND Leave open Connect to VDD via resistor Connect to VDD or GND via resistor Leave open Leave open Connect to VDD or GND via resistor HLDRQ# HLDACK# CKE RTCX1 RTCX2 CLKX1 CLKX2 FIRCLK BATTINH/ BATTINT# MPOWER POWERON POWER RSTSW# RTCRST# RxD TxD/CLKSEL2 RTS#/CLKSEL1 CTS# DCD#/GPIO15 DTR#/CLKSEL0 DSR# IRDIN IRDOUT# FIRDIN#/SEL DDIN/GPIO45 DDOUT/GPIO44 DRTS#/GPIO46 DCTS#/GPIO47 Note Intermediate-level input is enabled when the MPOWER pin is set for low-level output. Remarks 1. No specification (-) in the External Processing column indicates that the external processing is unnecessary. 2. No specification (-) in the Recommended Connection of Unused Pins column indicates that the pin is always connected. 22 Data Sheet U14691EJ1V0DS00 PD30121 (3/3) Pin Name Internal Processing Schmitt input, Pull down - - - - - - - Schmitt input, Note 2 Schmitt input, Note 2 Schmitt input, Note 2 Schmitt input, Note 2 Schmitt input, Note 2 Schmitt input, Note 2 Schmitt input - - - - - - - - - - - - - - - - - External Processing - - Note 1 - - - - - Note 2 Note 2 Note 2 Note 2 Note 2 Note 2 Pull down Pull down - - - Pull up/Pull down Pull up/Pull down - Note 3 - - - - - Pull up/Pull down Pull up/Pull down Pull up/Pull down Pull up/Pull down Drive Capability - 40 pF - 120 pF or more 120 pF or more 120 pF or more I/O Circuit Type B A F C D C E E B B B B B B B A A A A A A A A A A A A A A A A A Recommended Connection of Unused Pin Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Connect to VDD or GND via resistor Connect to VDD or GND Connect to VDD or GND Leave open Connect to VDD or GND Connect to VDD or GND via resistor Connect to GND Connect to GND Leave open Leave open Leave open Connect to GND Connect to GND Leave open Connect to GND Leave open Leave open Leave open Leave open Leave open - - - - KPORT (0:7) KSCAN (0:11)/ GPIO (32:43) AUDIOOUT TPX (0:1) TPY1 TPY0 ADIN (0:2) AUDIOIN GPIO (0:3) SRAS#/GPIO4 SCAS#/GPIO5 SYSDIR/GPIO6 SPOWER/GPIO7 GPIO (8:14) IRING ILCSENSE OFFHOOK MUTE AFERST# SDI FS SDO HSPSCLK TELCON HC0 HSPMCLK OPD# LEDOUT# DBUS32/GPIO48 MIPS16EN SMODE1/GPIO49 SMODE2 - - 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF - - 40 pF 40 pF 40 pF - - 40 pF - 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF 40 pF - - Notes 1. 2. Connect an operation amplifier which has high-impedance input characteristics, since the output level of AUDIOOUT pin varies according to the external impedance. If internal pull-up or pull-down resistors are used in GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, GPIO (8:14) pins switch between pull up, pull down, and open by software. If an internal pull-up or pull-down resistor is not used, then provide an external pull-up or pull-down resistor. 3. Input a synchronous clock from CODEC. Data Sheet U14691EJ1V0DS00 23 PD30121 Remarks 1. No specification (-) in the External Processing column indicates that the external processing is unnecessary. 2. No specification (-) in the Recommended Connection of Unused Pins column indicates that the pin is always connected. 1.4 Pin I/O Circuits Type A VDD Data P-ch IN/OUT Output disable Output disable N-ch Data Type D VDD P-ch IN/OUT N-ch P-ch + Input enable Type B Pullup enable VDD Data P-ch IN/OUT Type E Open drain Output disable N-ch IN N-ch P-ch + - Vref Pulldown enable Type F N-ch Analog output voltage OUT VDD - Vref N-ch P-ch Input enable N-ch Type C VDD Data P-ch IN/OUT Output disable N-ch P-ch + - Vref N-ch 24 Data Sheet U14691EJ1V0DS00 PD30121 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Symbol VDD2 VDD3 Input voltage VI Condition 2.5 V (VDDP, VDDPD, VDD2) 3.3 V (CVDD, DVDD, AVDD, PIUVDD, VDD3) VDD3 3.7 V VDD3 < 3.7 V Storage temperature Tstg Rating -0.5 to +3.3 -0.5 to +4.0 -0.5 to +4.0 -0.5 to VDD3 + 0.3 -65 to +150 Unit V V V V C Cautions 1. Do not short-circuit two or more output pins simultaneously. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The specifications and conditions shown in DC Characteristics and AC Characteristics are the ranges for normal operation and quality assurance of the product. 3. VI can be -1.5 V if the input pulse is less than 10 ns. Data Sheet U14691EJ1V0DS00 25 PD30121 Operating Conditions (1) 131 MHz model Parameter Supply voltage Symbol VDD2 VDD3 Ambient temperature Oscillation start voltage Oscillation hold voltage Oscillation hold voltage Note 1 Condition 2.5 V (VDDP, VDDPD, VDD2) 3.3 V (CVDD, DVDD, AVDD, PIUVDD, VDD3) MIN. 2.3 3.0 -10 MAX. 2.7 3.45 +70 3.0 2.5 3.0 Unit V V C V V V TA VDDS VDDH1 VDDH2 Note 2 Note 3 Notes 1. This is a voltage at which oscillation is always started after power application, and is applied to oscillators of 32.768 kHz and 18.432 MHz. 2. This is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal operation level, and is applied to an oscillator of 32.768 kHz. 3. This is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal operation level, and is applied to an oscillator of 18.432 MHz. (2) 168 MHz model Parameter Supply voltage Symbol VDD2 VDD3 Ambient temperature Oscillation start voltage Oscillation start voltage Oscillation start voltage Note 2 Condition 2.5 V (VDDP, VDDPD, VDD2) 3.3 V (CVDD, DVDD, AVDD, PIUVDD, VDD3) MIN. 2.6 3.0 -10 MAX. 2.7 Note 1 Unit V V C V V V 3.45 +70 3.0 2.5 3.0 TA VDDS VDDH1 VDDH2 Note 3 Note 4 Notes 1. If VDD2 exceeds 2.7 V, be sure to keep the time for which the voltage is exceeded to less than 10 % of the total operating time of the VR4121, and the maximum value of VDD2 to less than 2.8 V. 2. This is a voltage at which oscillation is always started after power application, and is applied to oscillators of 32.768 kHz and 18.432 MHz. 3. This is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal operation level, and is applied to an oscillator of 32.768 kHz. 4. This is a voltage at which oscillation can be guaranteed if the voltage is lowered from the normal operation level, and is applied to an oscillator of 18.432 MHz. Capacitance (TA = 25C, VDD = 0 V) Parameter Input capacitance I/O capacitance Symbol CI CIO Condition fC = 1 MHz Unmeasured pins returned to 0 V. MIN. MAX. 10 10 Unit pF pF Caution Precision tests have not been performed. Only guaranteed as design characteristics. 26 Data Sheet U14691EJ1V0DS00 PD30121 DC Characteristics (1) 131 MHz model (TA = -10 to +70C, VDD2 = 2.3 to 2.7 V, VDD3 = 3.0 to 3.45 V) (1/2) Parameter Output voltage, high Output voltage, high Output voltage, low Note 1 Symbol VOH1 VOH2 VOL1 IOH = -2 mA Condition MIN. 0.8VDD3 0.8VDD3 TYP. MAX. Unit V V IOH = -12 mA IOL = 2 mA IOL = 20 A 0.4 0.1 0.4 0.1 0.8 VDD3 -0.3 2.0 -0.3 0.75VDD3 -0.3 0.17VDD3 VDD3 + 0.3 0.3 VDD3 VDD3 + 0.3 0.3VDD3 VDD3 + 0.3 0.6 V Output voltage, low Note 1 VOL2 IOL = 12 mA IOL = 20 A V Clock input voltage, high Clock input voltage, low Input voltage, high Input voltage, low Note 3 Note 2 VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VH ILI VDD3 = 3.45 V, VI = VDD3, 0 V VDD3 = 3.45 V, VI = VDD3 VDD3 = 3.45 V, VI = 0 V VDD3 = 3.45 V, VI = VDD3, 0 V V V V V V V V Note 2 Note 3 Input voltage, high Input voltage, low Note 4 Note 4 Hysteresis voltage Note 4, 5 Input leakage current Note 6 5 72 -72 5 A A A A Input leakage current, high Input leakage current, low Output leakage current Note 7 ILIH ILIL ILO Note 8 Notes 1. Applied to TPX (0:1), TPY (0:1). A panel resistance of 250 is presumed. 2. Applies to FIRCLK and HSPSCLK pins. 3. Except RTCX1, CLKX1, FIRCLK, HSPSCLK, TPX (0:1), TPY (0:1), ADIN (0:2), AUDIOIN, POWER, RSTSW#, RTCRST#, GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYDIR/GPIO6, SPOWER/GPIO7, GPIO (8:14), DCD#/GPIO15, BATTINH/BATTINT#, IRING, and KPORT (0:7) pins. 4. Applied to POWER, RSTSW#, RTCRST#, GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYDIR/GPIO6, SPOWER/GPIO7, GPIO (8:14), DCD#/GPIO15, BATTINH/BATTINT#, IRING, and KPORT (0:7) pins. 5. Hysteresis voltage: Difference between the minimum voltage at which the high level of a Schmitt input signal is not recognized when the signal goes from low to high and the maximum voltage at which the low level is not recognized when the signal goes from high to low. 6. Except KPORT (0:7) (input pins with pull-down resistor), TPX (0:1), and TPY (0:1) pins. 7. Applied to KPORT (0:7) pin (input pins with pull-down resistor), GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, and GPIO (8:14) pins when the internal pull-down resistor is used. 8. Applied to GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, and GPIO (8:14) pins when the internal pull-up resistor is used. Data Sheet U14691EJ1V0DS00 27 PD30121 (2/2) Parameter Power supply current Symbol IDD2 Note 2 Condition In Fullspeed mode In Standby mode In Suspend mode In Hibernate mode, VDD2 = 0.0 V, when LED unit is off. MIN. TYP. Note 1 MAX. 340 100 30 0 Unit mA mA mA 140 50 15 0 A IDD3 Note 3 In Fullspeed mode, ADD (0:24), ADD25/SCLK, CKE, RD#, WR#, TPX (0:1), TPY (0:1) = 120 pF, other pins = 40 pF In Standby mode, external load 0 pF In Suspend mode, external load 0 pF In Hibernate mode, external load 0 pF, when LED unit is off. 30 60 mA 10 3 100 30 9 500 mA mA A Notes 1. Unless otherwise specified, these are reference values at TA = 25C, VDD2 = 2.5 V, VDD3 = 3.3 V. 2. Total current flowing to the VDDP, VDDPD, and VDD2 pins. 3. Total current flowing to the CVDD, DVDD, AVDD, PIUVDD, and VDD3 pins. Remark IDD2 and IDD3 do not reach the maximum value at the same time in the Fullspeed mode. 28 Data Sheet U14691EJ1V0DS00 PD30121 (2) 168 MHz model (TA = -10 to +70C, VDD2 = 2.6 to 2.7 V, VDD3 = 3.0 to 3.45 V) (1/2) Parameter Output voltage, high Output voltage, high Output voltage, low Note 1 Symbol VOH1 VOH2 VOL1 IOH = -2 mA Condition MIN. 0.8VDD3 0.8VDD3 TYP. MAX. Unit V V IOH = -12 mA IOL = 2 mA IOL = 20 A 0.4 0.1 0.4 0.1 0.8 VDD3 -0.3 2.0 -0.3 0.75VDD3 -0.3 0.17VDD3 VDD3 + 0.3 0.3 VDD3 VDD3 + 0.3 0.3VDD3 VDD3 + 0.3 0.6 V Output voltage, low Note 1 VOL2 IOL = 12 mA IOL = 20 A V Clock input voltage, high Clock input voltage, low Input voltage, high Input voltage, low Note 3 Note 2 VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VH ILI VDD3 = 3.45 V, VI = VDD3, 0 V VDD3 = 3.45 V, VI = VDD3 VDD3 = 3.45 V, VI = 0 V VDD3 = 3.45 V, VI = VDD3, 0 V V V V V V V V Note 2 Note 3 Input voltage, high Input voltage, low Note 4 Note 4 Hysteresis voltage Note 4, 5 Input leakage current Note 6 5 72 -72 5 A A A A Input leakage current, high Input leakage current, low Output leakage current Note 7 ILIH ILIL ILO Note 8 Notes 1. Applied to TPX (0:1), TPY (0:1). A panel resistance of 250 is presumed. 2. Applies to FIRCLK and HSPSCLK pins. 3. Except RTCX1, CLKX1, FIRCLK, HSPSCLK, TPX (0:1), TPY (0:1), ADIN (0:2), AUDIOIN, POWER, RSTSW#, RTCRST#, GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYDIR/GPIO6, SPOWER/GPIO7, GPIO (8:14), DCD#/GPIO15, BATTINH/BATTINT#, IRING, and KPORT (0:7) pins. 4. Applied to POWER, RSTSW#, RTCRST#, GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYDIR/GPIO6, SPOWER/GPIO7, GPIO (8:14), DCD#/GPIO15, BATTINH/BATTINT#, IRING, and KPORT (0:7) pins. 5. Hysteresis voltage: Difference between the minimum voltage at which the high level of a Schmitt input signal is not recognized when the signal goes from low to high and the maximum voltage at which the low level is not recognized when the signal goes from high to low. 6. Except KPORT (0:7) (input pins with pull-down resistor), TPX (0:1), and TPY (0:1) pins. 7. Applied to KPORT (0:7) pin (input pins with pull-down resistor), GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, and GPIO (8:14) pins when the internal pull-down resistor is used. 8. Applied to GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, and GPIO (8:14) pins when the internal pull-up resistor is used. Data Sheet U14691EJ1V0DS00 29 PD30121 (2/2) Parameter Power supply current Symbol IDD2 Note 2 Condition In Fullspeed mode In Standby mode In Suspend mode In Hibernate mode, VDD2 = 0.0 V, when LED unit is off. MIN. TYP. Note 1 MAX. 370 100 30 0 Unit mA mA mA 180 50 15 0 A IDD3 Note 3 In Fullspeed mode, ADD (0:24), ADD25/SCLK, CKE, RD#, WR#, TPX (0:1), TPY (0:1) = 120 pF, other pins = 40 pF In Standby mode, external load 0 pF In Suspend mode, external load 0 pF In Hibernate mode, external load 0 pF, when LED unit is off. 30 60 mA 10 3 100 30 9 500 mA mA A Notes 1. Unless otherwise specified, these are reference values at TA = 25C, VDD2 = 2.6 V, VDD3 = 3.3 V. 2. Total current flowing to the VDDP, VDDPD, and VDD2 pins. 3. Total current flowing to the CVDD, DVDD, AVDD, PIUVDD, and VDD3 pins. Remark IDD2 and IDD3 do not reach the maximum value at the same time in the Fullspeed mode. 30 Data Sheet U14691EJ1V0DS00 PD30121 Data Retention Characteristics (TA = 25C) Parameter Data retention voltage Note 1 Symbol VDDDR3 Note 2 Condition Hibernate mode, 3.3 V power supply MIN. 2.5 0.9VDDDR3 MAX. 3.45 Unit V V Data retention input voltage, high VIHDR Notes 1. The data retention voltage is the voltage at which the operation of the Elapsed Time timer and the data retention of the registers of the following peripheral units are guaranteed, and is not applied to the internal data of the CPU core. BCU: BCURFCNTREG, BCUCNTREG3, SDRAMMODEREG, SROMMODEREG, SDRAMCNTREG PUM: PMUCNTREG (15:8), PMUCNT2REG, PMUWAITREG, PMUDIVREG RTC: ETIMELREG, ETIMEMREG, ETIMEHREG, ECMPLREG, ECMPMREG, ECMPHREG, RTCL1LREG, RTCL1HREG, RTCL1CNTLREG, RTCL1CNTHREG, RTCL2LREG, RTCL2HREG, RTCL2CNTLREG, RTCL2CNTHREG, RTCINTREG (2:0) GIU: GIUPODATL, GIUPODATH, GIUUSEUPNL, GIUTERMUPNL KIU: KIUGPEN, PORTREG LED: LEDHTSREG, LEDLTSREG, LEDHLTCLREG, LEDHLTCHREG, LEDCNTREG 2. Applied to RTCRST# pin. Remark The values in parentheses are the targeted values. Data Sheet U14691EJ1V0DS00 31 PD30121 AC Characteristics (131 MHz model: TA = -10 to +70C, VDD2 = 2.3 to 2.7 V, VDD3 = 3.0 to 3.45 V 168 MHz model: TA = -10 to +70C, VDD2 = 2.6 to 2.7 V, VDD3 = 3.0 to 3.45 V) AC test input waveform (a) CTS#, DATA (0:15), DATA (16:31)/GPIO (16:31), DBUS32/GPIO48, DCTS#/GPIO47, DDIN/GPIO45, DSR#, DTR#/CLKSEL0, FS, FIRDIN#/SEL, HLDRQ#, ILCSENSE, IOCHRDY, IOCS16#, IRDIN, LCDRDY, MEMCS16#, RxD, RTS#/CLKSEL1, SDI, SMODE1/GPIO49, SMODE2, TxD/CLKSEL2, ZWS# VDD 2.0 V Test points 0.3 V 2.0 V 0.3 V 0V (b) BATTINH/BATTINT#, DCD#/GPIO15, GPIO (0:3), GPIO (8:14), IRING, KPORT (0:7), POWER, RSTSW#, RTCRST#, SCAS#/GPIO5, SPOWER/GPIO7, SRAS#/GPIO4, SYSDIR/GPIO6 VDD 0.75VDD Test points 0.2 V 0V 0.2 V 0.75VDD AC test output measuring points (c) ADD (0:24), ADD25/SCLK, AFERST#, BUSCLK, CKE, DATA (0:15), DATA (16:31)/GPIO (16:31), DBUS32/GPIO48, DCTS#/GPIO47, DDIN/GPIO45, DDOUT/GPIO44, DRTS#/GPIO46, DTR#/CLKSEL0, FIRDIN#/SEL, GPIO (0:3), GPIO (8:14), HC0, HLDACK#, HSPMCLK, IOR#, IOW#, IRDOUT#, KSCAN (0:11)/GPIO (32:43), LCAS#, LCDCS#, LEDOUT#, MEMR#, MEMW#, MPOWER, MRAS (0:1)#, MUTE, OFFHOOK, OPD#, POWERON, RD#, ROMCS (0:3)#, RSTOUT, RTS#/CLKSEL1, SCAS#/GPIO5, SDO, SHB#, SMODE1/GPIO49, SPOWER/GPIO7, SRAS#/GPIO4, SYSDIR/GPIO6, TELCON, TPX (0:1), TPY (0:1), TxD/CLKSEL2, UCAS#, ULCAS#/MRAS2#, UUCAS#/MRAS3#, WR# VDD 0.5VDD 0V Test points 0.5VDD 32 Data Sheet U14691EJ1V0DS00 PD30121 Load condition (a) ADD (0:24), ADD25/SCLK, CKE, RD#, WR#, TPX (0:1), TPY (0:1) ADD (0:24), ADD25/SCLK, CKE, RD#, WR#, TPX (0:1), TPY (0:1) DUT CL = 120 pF (b) Other output pins Output pin (other than those shown in (a)) DUT CL = 40 pF Data Sheet U14691EJ1V0DS00 33 PD30121 (1) Clock parameter (1/2) Parameter HSPSCLK high-level width HSPSCLK low-level width HSPSCLK clock frequency HSPSCLK clock cycle HSPSCLK clock rise time HSPSCLK clock fall time HSPMCLK high-level width HSPMCLK low-level width HSPMCLK clock frequency HSPMCLK clock cycle FIRCLK clock frequency Symbol tWHSH tWHSL fHSCYC tCYHS tHSR tSHF tMPH tMPL fMCYC tCYHM fFIRCYC1 fFIRCYC2 FIRCLK clock duty SCLK high-level width SCLK low-level width SCLK jitter Note 2 Note 1 Note 1 Condition When HSP unit is used When HSP unit is used When HSP unit is used When HSP unit is used When HSP unit is used When HSP unit is used When HSP unit is used When HSP unit is used When HSP unit is used When HSP unit is used In FIR 4 Mbps In FIR 1.152/0.576 Mbps MIN. 40 40 TYP. MAX. Unit ns ns fMCYC 108.5 10 10 tCYHM x 0.45 tCYHM x 0.45 0.585 54.253 47.99520 47.93800 10 3.5 3.5 3.5 48 48 tCYHM x 0.55 tCYHM x 0.55 18.432 1790.365 48.00480 48.02976 90 MHz ns ns ns ns ns MHz ns MHz MHz % ns ns % MHz MHz MHz MHz MHz MHz MHz MHz ns ns ns ns tFIRDUTY tCH tCL tJitter fPCYC CLKSEL (2:0) = 111 CLKSEL (2:0) = 110 CLKSEL (2:0) = 101 CLKSEL (2:0) = 100 CLKSEL (2:0) = 011 CLKSEL (2:0) = 010 CLKSEL (2:0) = 001 CLKSEL (2:0) = 000 Note 3 CPU core operating frequency RFU 168.5 147.5 131.1 118.0 98.3 90.7 78.6 45 10 45 10 Note 4 Note 4 BUSCLK high-level width tBCLKH1 tBCLKH2 Note 5 Note 6 Note 5 Note 6 BUSCLK low-level width tBCLKL1 tBCLKL2 Notes 1. Applied to ADD25/SCLK pin. 2. Precision tests have not been performed. Only guaranteed as design characteristics. 3. Do not set CLKSEL (2:0) = 111. 4. The settings CLKSEL (2:0) = 110 and 101 are only guaranteed for the 168 MHz model. Do not apply these settings to the 131 MHz model. 5. Applied to BUSCLK pin when BSEL bit of BCUCNTREG3 register is 0. 6. Applied to BUSCLK pin when BSEL bit of BCUCNTREG3 register is 1. Remark CLKSEL (2:0): Value set to the TxD/CLKSEL2, RTS#/CLKSEL1, and DTR#/CLKSEL0 pins after reset. 34 Data Sheet U14691EJ1V0DS00 PD30121 (1) Clock parameter (2/2) tCYHS tWHSH HSPSCLK (input) tHSR tSHF tCYHM tMPH HSPMCLK (output) tCH SCLK (output) tBCLKH1 tBCLKH2 BUSCLK (output) tBCLKL1 tBCLKL2 tCL tMPL tWHSL Data Sheet U14691EJ1V0DS00 35 PD30121 (2) Reset parameter Parameter Reset input low-level width Symbol tWRSL RTCRST# Condition MIN. 305 MAX. Unit s tWRSL RTCRST# (input) Remark For the RTCRST# characteristics at power application, refer to VR4121 User's Manual. (3) Initialization parameter Parameter Data sampling time (from RTCRST# ) Output delay time (from RTCRST# ) Symbol tSS tOD 61.04 Condition MIN. MAX. 61.04 Unit s s RTCRST# (input) tSS Hi-Z Input tOD TxD/CLKSEL2 RTS#/CLKSEL1 DTR#/CLKSEL0 (I/O) DBUS32/GPIO48 MIPS16EN SMODE1/GPIO49 SMODE2 (input) , Don t care Output Hi-Z Hi-Z Sampling Remark Set the input data level by using a pull-up or pull-down resistor with high resistance. 36 Data Sheet U14691EJ1V0DS00 PD30121 (4) GPIO interface parameter (1/2) Parameter Input level width Symbol tINP1 tINP2 tINP3 GPIO input rise time tGPINR1 tGPINR2 GPIO input fall time tGPINF1 tGPINF2 Output level width tOUTP Note 1 Note 2 Note 3 Note 4 Note 5 Note 4 Note 5 Note 6 30 Condition MIN. 91.5 361.5 180.6 200 10 200 10 MAX. Unit s ns ns ns ns ns ns ns Notes 1. Applied to GPIO (0:3) pins. 2. Applied to GPIO (9:14) and DCD#/GPIO15 pins. 3. Applied to SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, GPIO8, and DATA (16:31)/GPIO (16:31) pins. 4. Applied to GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, GPIO (8:14), and DCD#/GPIO15 pins. 5. Applied to DATA (16:31)/GPIO (16:31) pins. 6. Applied to GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, GPIO (8:14), DATA (16:31)/GPIO (16:31), KSCAN (0:11)/GPIO (32:43), DDOUT/GPIO44, DDIN/GPIO45, DRTS#/ GPIO46, DCTS#/GPIO47, DBUS32/GPIO48, and SMODE1/GPIO49 pins. Caution These parameters are applied when the SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, DCD#/GPIO15, DATA (16:31)/GPIO (16:31), KSCAN (0:11)/GPIO (32:43), DDOUT/ GPIO44, DDIN/GPIO45, DRTS#/GPIO46, DCTS#/GPIO47, DBUS32/GPIO48, or SMODE1/GPIO49 pin is used as the GPIO signal. Data Sheet U14691EJ1V0DS00 37 PD30121 (4) GPIO interface parameter (2/2) (a) Input level width tINP1 Note 1 tINP2 Note 2 tINP3 Note 3 Notes 1. GPIO (0:3) pins 2. GPIO (9:14), DCD#/GPIO15 pins 3. SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, GPIO8, DATA (16:31)/GPIO (16:31) pins (b) GPIO input rise/fall time tGPINF1 Note 1 tGPINF2 Note 2 tGPINR1 Note 1 tGPINR2 Note 2 Notes 1. GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, GPIO (8:14), DCD#/ GPIO15 pins 2. DATA (16:31)/GPIO (16:31) pins (c) Output level width tOUTPNote Note GPIO (0:3), SRAS#/GPIO4, SCAS#/GPIO5, SYSDIR/GPIO6, SPOWER/GPIO7, GPIO (8:14), DATA (16:31)/GPIO (16:31), KSCAN (0:11)/GPIO (32:43), DDOUT/GPIO44, DDIN/GPIO45, DRTS#/GPIO46, DCTS#/GPIO47, DBUS32/GPIO48, SMODE1/GPIO49 pins 38 Data Sheet U14691EJ1V0DS00 PD30121 (5) EDO-type DRAM read parameter (1/2) The target DRAM is the PD42S16165L-A60, 42S18165L-A60, 42S64165G5-A50, 42S64165G5-A60, 42S65165G5-A50, or 42S65165G5-A60. Parameter MRAS (0:3)# pulse width MRAS (0:3)# hold time (from UCAS#/LCAS# precharge) MRAS (0:3)# precharge time UCAS#/LCAS# hold time (from MRAS (0:3)#) UCAS#/LCAS# pulse width UCAS#/LCAS# precharge time Read/write cycle time MRAS (0:3)# hold time (from UCAS#/LCAS#) Row address setup time (to MRAS (0:3)#) UCAS#/LCAS# delay time from MRAS (0:3)# Column address delay time from MRAS (0:3)# Column address setup time (to UCAS#/LCAS#) Column address read time (to MRAS (0:3)#) Row address hold time (from MRAS (0:3)# ) Column address hold time 1 (from UCAS#/LCAS# ) Column address hold time 2 (from UCAS#/LCAS# ) Column address hold time 3 (from UCAS#/LCAS# ) Data access time (from UCAS#/LCAS# precharge) Data access time (from RD# ) Data input setup time 1 (to UCAS#/LCAS# ) Data input hold time 1 (from MRAS (0:3)#) Data input setup time 2 (to UCAS#/LCAS# ) Data input hold time 2 (from MRAS (0:3)#) Data access time (from MRAS (0:3)# ) Data access time (from column address) Data access time (from UCAS#/LCAS# ) Symbol tRASP tRHCP tRP tCSH tHCAS tCP tHPC tRSH tASR tRCD tRAD tASC tRAL tRAH tCAH1 tCAH2 tCAH3 tACP tOEA tDS1 tDH1 tDS2 tDH2 tRAC tAA tCAC Condition MIN. 70 45 43 50 10 10 25 25 0 24 22 0 40 20 10 10 10 39 25 0 5 0 5 70 30 20 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Caution These ratings are applied only when a device operates within the recommended operating condition range and the operating ambient temperature is kept constant. If the power supply voltage or operating ambient temperature changes during DRAM access, the above ratings are not applied. Data Sheet U14691EJ1V0DS00 39 PD30121 (5) EDO-type DRAM read parameter (2/2) MRAS (0:3)#Note 1 (output) tCSH UCAS#/LCAS#Note 2 (output) tASR ADD (19:23) (output) tRAD ADD (9:18) (output) RD# (output) tRAH tASC tRCD tRASP tRHCP tHCAS tCP tHPC tRSH tRP tCAH3 tCAH1 tRAL tCAH2 tOEA DATANote 3 (I/O) Invalid tDS1 tRAC tAA tCAC tACP tDH1 tDS2 tDH2 Invalid Notes 1. In 32-bit mode: Applied to MRAS (0:1)# pins In 16-bit mode: Applied to UUCAS#/MRAS3#, ULCAS#/MRAS2#, and MRAS (0:1)# pins 2. In 32-bit mode: Applied to UUCAS#/MRAS3#, ULCAS#MRAS2#, UCAS#, and LCAS# pins In 16-bit mode: Applied to UCAS# and LCAS# pins 3. In 32-bit mode: Applied to DATA (16:31)/GPIO (16:31) and DATA (0:15) pins In 16-bit mode: Applied to DATA (0:15) pins Remark The broken lines indicate high impedance. 40 Data Sheet U14691EJ1V0DS00 PD30121 (6) EDO-type DRAM write parameter (1/2) The target DRAM is the PD42S16165L-A60, 42S18165L-A60, 42S64165G5-A50, 42S64165G5-A60, 42S65165G5-A50, or 42S65165G5-A60. Parameter MRAS (0:3)# pulse width MRAS (0:3)# hold time (from UCAS#/LCAS# precharge) MRAS (0:3)# precharge time UCAS#/LCAS# hold time (from MRAS (0:3)# ) UCAS#/LCAS# pulse width UCAS#/LCAS# precharge time Read/write cycle time MRAS (0:3)# hold time (from UCAS#/LCAS#) Row address setup time (to MRAS (0:3)# ) UCAS#/LCAS# delay time from MRAS (0:3)# Column address delay time from MRAS (0:3)# Column address setup time (to UCAS#/LCAS# ) Column address read time (to MRAS (0:3)# ) Row address hold time (from MRAS (0:3)# ) Column address hold time 1 (from UCAS#/LCAS# ) Column address hold time 2 (from UCAS#/LCAS# ) Column address hold time 3 (from UCAS#/LCAS# ) WR# setup time WR# hold time (from UCAS#/LCAS# ) Data output setup time Data output hold time Symbol tRASP tRHCP tRP tCSH tHCAS tCP tHPC tRSH tASR tRCD tRAD tASC tRAL tRAH tCAH1 tCAH2 tCAH3 tWCS tWCH tD1 tD2 Condition MIN. 70 45 43 50 10 10 25 25 0 24 22 0 40 20 10 10 10 0 20 0 10 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Caution These ratings are applied only when a device operates within the recommended operating condition range and the operating ambient temperature is kept constant. If the power supply voltage or operating ambient temperature changes during DRAM access, the above ratings are not applied. Data Sheet U14691EJ1V0DS00 41 PD30121 (6) EDO-type DRAM write parameter (2/2) MRAS (0:3)#Note 1 (output) tCSH UCAS#/LCAS#Note 2 (output) tASR ADD (19:23) (output) tRAD ADD (9:18) (output) WR# (output) DATANote 3 (I/O) tRAH tRCD tRASP tRHCP tHCAS tCP tHPC tRSH tRP tCAH3 tASC tRAL tCAH1 tWCS tD1 Invalid tD2 tD1 tCAH2 tWCH tD2 Notes 1. In 32-bit mode: Applied to MRAS (0:1)# pins In 16-bit mode: Applied to UUCAS#/MRAS3#, ULCAS#/MRAS2#, and MRAS (0:1)# pins 2. In 32-bit mode: Applied to UUCAS#/MRAS3#, ULCAS#MRAS2#, UCAS#, and LCAS# pins In 16-bit mode: Applied to UCAS# and LCAS# pins 3. In 32-bit mode: Applied to DATA (16:31)/GPIO (16:31) and DATA (0:15) pins In 16-bit mode: Applied to DATA (0:15) pins 42 Data Sheet U14691EJ1V0DS00 PD30121 (7) DRAM refresh parameter The target DRAM is the PD42S161615L-A60, 42S18165L-A60, 42S64165G5-A50, 42S64165G5-A60, 42S65165G5-A50, or 42S65165G5-A60. (a) CAS-before-RAS refresh parameter Parameter Read/write cycle time MRAS (0:3)# pulse width MRAS (0:3)# precharge time UCAS#/LCAS# setup time (to MRAS (0:3)# ) UCAS#/LCAS# hold time (from MRAS (0:3)# ) MRAS (0:3)# precharge time from UCAS#/LCAS# UCAS#/LCAS# precharge time Symbol tRC tRAS tRP tCSR tCHR tCRP tCPN Condition MIN. 104 60 30 5 10 5 10 MAX. Unit ns ns ns ns ns ns ns tRC MRAS (0:3)#Note 1 (output) tCSR tRAS tRP tCRP UCAS#/LCAS#Note 2 (output) tCHR tCPN WR# H (output) Notes 1. In 32-bit mode: Applied to MRAS (0:1)# pins In 16-bit mode: Applied to UUCAS#/MRAS3#, ULCAS#/MRAS2#, and MRAS (0:1)# pins 2. In 32-bit mode: Applied to UUCAS#/MRAS3#, ULCAS#MRAS2#, UCAS#, and LCAS# pins In 16-bit mode: Applied to UCAS# and LCAS# pins Data Sheet U14691EJ1V0DS00 43 PD30121 (b) CAS-before-RAS self-refresh parameter Parameter MRAS (0:3)# pulse width Note Symbol tRASS tRPS tCHS Condition MIN. 100 110 -50 MAX. Unit s ns ns MRAS (0:3)# precharge time UCAS#/LCAS# hold time Note The CAS-before-RAS self-refresh parameter is valid when tRASS exceeds 100 s. tRASS MRAS (0:3)#Note 1 (output) tCHS tRPS UCAS#/LCAS#Note 2 (output) Notes 1. In 32-bit mode: Applied to MRAS (0:1)# pins In 16-bit mode: Applied to UUCAS#/MRAS3#, ULCAS#/MRAS2#, and MRAS (0:1)# pins 2. In 32-bit mode: Applied to UUCAS#/MRAS3#, ULCAS#MRAS2#, UCAS#, and LCAS# pins In 16-bit mode: Applied to UCAS# and LCAS# pins 44 Data Sheet U14691EJ1V0DS00 PD30121 (8) Normal ROM parameter (1/2) Parameter Data access time (from address) Note Symbol tACC Note Condition MIN. T x N - 19 T x N - 19 T x (N - 1) - 29 0 5 MAX. Unit ns ns ns ns ns Data access time (from ROMCS (0:3)# ) Data access time (from RD#) Data input setup time Data input hold time Note tCE tOE tDS tDH Note The value of N is set by using the WROMA (0:2) bits of the BCUSPEEDREG register. The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and DTR#/CLKSEL0 pins). CLKSEL2 Signal 1 1 1 1 0 0 0 0 CLKSEL1 Signal 1 1 0 0 1 1 0 0 CLKSEL0 Signal 1 0 1 0 1 0 1 0 WROMA2 Bit 0 0 0 0 1 1 1 1 WROMA1 Bit 0 0 1 1 0 0 1 1 WROMA0 Bit 0 1 0 1 0 1 0 1 N (TClock) 9 8 7 6 5 4 3 2 T (ns) RFU 35 33 30 33 30 33 38 Remarks 1. Do not set CLKSEL (2:0) signal = 111. 2. Do not set CLKSEL (2:0) signal = 110, 101 with 131 MHz model. Data Sheet U14691EJ1V0DS00 45 PD30121 (8) Normal ROM parameter (2/2) When WROMA (0:2) bits = 111 ADD (19:23), ADD (0:8) (output) ADD (9:18) (output) tACC ROMCS (0:3)# (output) tCE RD# (output) tOE DATA Note (I/O) Invalid Invalid tDS tDH Note In 32-bit mode: Applied to DATA (16:31)/GPIO (16:31) and DATA (0:15) pins In 16-bit mode: Applied to DATA (0:15) pins Remark The broken lines indicate high impedance. 46 Data Sheet U14691EJ1V0DS00 PD30121 (9) Page ROM parameter (1/2) Parameter Data access time (from address) Note Symbol tACC1 tACC2 Note Condition MIN. T x N - 19 T x M - 18 T x N - 19 T x (N - 1) - 29 0 5 MAX. Unit ns ns ns ns ns ns Data access time (from ROMCS (0:3)# ) Data access time (from RD#) Data input setup time Data input hold time Note tCE tOE tDS tDH Note The value of N is set by using the WROMA (0:2) bits of the BCUSPEEDREG register. The value of M is set by using the WPROM (0:1) bits of the BCUSPEEDREG register. The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and DTR#/CLKSEL0 pins). CLKSEL 2 CLKSEL 1 CLKSEL 0 Signal Signal Signal 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 WROMA 2 WROMA 1 WROMA 0 N Bit Bit Bit (TClock) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 9 8 7 6 5 4 3 2 WPROM WPROM M 1 Bit 0 Bit (TClock) 0 0 1 1 0 1 0 1 3 2 1 T (ns) RFU 35 33 30 33 30 33 38 Remarks 1. Do not set CLKSEL (2:0) signal = 111. 2. Do not set CLKSEL (2:0) signal = 110, 101 with 131 MHz model. Data Sheet U14691EJ1V0DS00 47 PD30121 (9) Page ROM parameter (2/2) ADD (1:3) (output) ADD (4:23), ADD0 (output) tACC1 ROMCS (0:3)# (output) tCE RD# (output) tOE DATA (I/O) Note tACC2 Invalid tDS tDH tDS tDH Invalid Note In 32-bit mode: Applied to DATA (16:31)/GPIO (16:31) and DATA (0:15) pins In 16-bit mode: Applied to DATA (0:15) pins Remark The broken lines indicate high impedance. 48 Data Sheet U14691EJ1V0DS00 PD30121 (10) Flash memory mode write parameter Parameter Write cycle time Address setup time (to WR# ) Address setup time (to ROMCS (0:3)# ) ROMCS (0:3)# setup time (to WR#) WR# low-level width ROMCS (0:3)# hold time (from WR# ) Address hold time (from WR# ) WR# high-level width Address setup time (to WR# ) Data output setup time (to WR# ) Data output hold time (from WR# ) Symbol tAVAV tAVWH tAVEL tELWL tWLWH tWHEH tWHAX tWHWL tAVWL tDVWH tWHDX Condition MIN. 150 75 0 10 75 10 10 75 25 75 10 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ADD (19:23), ADD (0:8) (output) ADD (9:18) (output) tAVAV tAVWH ROMCS (0:3)# (output) tAVEL WR# (output) DATA Note (I/O) tELWL tWLWH tAVWL Invalid tDVWH tWHDX tWHEH tWHWL tWHAX Note In 32-bit mode: Applied to DATA (16:31)/GPIO (16:31) and DATA (0:15) pins In 16-bit mode: Applied to DATA (0:15) pins Data Sheet U14691EJ1V0DS00 49 PD30121 (11) Flash memory mode read parameter Parameter Data output delay time from address Data output delay time from ROMCS (0:3)# Address setup time (to ROMCS (0:3)# ) Data output delay time from RD# Address setup time (to RD# ) ROMCS (0:3)# hold time (from RD# ) Address hold time (from RD# ) RD# high-level width Data input setup time Data input hold time ROMCS (0:3)# setup time (to RD# ) Symbol tAVQV tELQV tAVEL tGLQV tAVGL tGHEH tGHAX tGHGL tDS tDH tELGL Condition MIN. 180 180 0 80 0 10 10 75 0 5 10 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ADD (19:20), ADD (0:8) (output) ADD (9:18) (output) tGHAX ROMCS (0:3)# (output) RD# (output) tAVGL DATA Note (I/O) Invalid tDS tGLQV tELQV tALQV tDH Invalid tAVEL tELGL tGHEH tGHGL Note In 32-bit mode: Applied to DATA (16:31)/GPIO (16:31) and DATA (0:15) pins In 16-bit mode: Applied to DATA (0:15) pins Remark The broken lines indicate high impedance. 50 Data Sheet U14691EJ1V0DS00 PD30121 (12) System bus parameter (IOCHRDY) (1/3) Parameter BUSCLK high-level width Symbol tBCLKH1 tBCLKH2 BUSCLK low-level width tBCLKL1 tBCLKL2 Address setup time (to BUSCLK) Address setup time (to command signal ) Command signal setup time (to BUSCLK) Command signal low-level width Notes 3, 4 Note 3 Notes 3, 4 Condition Note 1 Note 2 Note 1 Note 2 MIN. 45 10 45 10 15 T x N - 29 15 2 x T x N - 29 25 T x (N + 1) - 29 0 TxN 0 0 25 2 x T x N - 44 0 0 5 MAX. Unit ns ns ns ns ns ns ns ns ns ns tAVCK tAVCL tCLCK tCLCH tCHAV tCHCL tCLR Notes 3, 4 Note 3 Address hold time (from command signal ) Command signal recovery time IOCHRDY sampling time Note 4 Notes 3, 4 T x N - 44 2 x T x N + 29 ns ns ns ns ns ns ns ns ns Command signal delay time from IOCHRDY IOCHRDY hold time (from command signal ) Data output setup time (to command signal ) tRHCH tCHRL tDVCL tCHDV tAVSV1 tCHSV tDS tDH Note 3 Note 3 Note 3 Data output hold time (from command signal ) MEMCS16#/IOCS16# sampling start time signal ) Note 3 Note 4 MEMCS16#/IOCS16# hold time (from command Data input setup time Data input hold time Notes 1. Applied to BUSCLK pin when BSEL bit of BCUCNTREG3 register is 0. 2. Applied to BUSCLK pin when BSEL bit of BCUCNTREG3 register is 1. 3. With the VR4121, the MEMW#, MEMR#, IOW#, and IOR# signals are called the command signals for the system bus interface. 4. The value of N is set by using the WISAA (0:2) bits of the BCUSPEEDREG register. The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and DTR#/CLKSEL0 pins). CLKSEL2 Signal 1 1 1 1 0 0 0 0 CLKSEL1 Signal 1 1 0 0 1 1 0 0 CLKSEL0 Signal 1 0 1 0 1 0 1 0 T (ns) RFU 35 33 30 33 30 33 38 WISAA2 Bit 0 0 0 0 1 1 Note Note WISAA1 Bit 0 0 1 1 0 0 Note Note WISAA0 Bit 0 1 0 1 0 1 Note Note N (TClock) 8 7 6 5 4 3 1 1 1 1 0 1 Remarks 1. Do not set CLKSEL (2:0) signal = 111. 2. Do not set CLKSEL (2:0) signal = 110, 101 with 131 MHz model. Note If the WISAA (0:2) bits are set to 100 or high when BSEL bit of BCUCNTREG3 register is 0, the AC characteristics of tAVCK and tCLCK are not guaranteed. Data Sheet U14691EJ1V0DS00 51 PD30121 (12) System bus parameter (IOCHRDY) (2/3) When WISAA (0:2) bits = 010, BSEL bit = 0 tBCLKH1 tBCLKL1 BUSCLKNote 1 (output) BUSCLKNote 1 (output) BUSCLKNote 1 (output) BUSCLKNote 1 (output) ADD (19:25), ADD (0:8) (output) ADD (9:18) (output) tAVCL SHB# (output) MEMR#/MEMW#, IOR#/IOW# (output) IOCHRDY (input) ZWS# (input) tAVSV1 MEMCS16#, IOCS16# (input) DATA (output) DATA (input) Invalid tDS Invalid tDH Invalid tCHSV tCLCKNote 2 tCLCH tCLR tRHCH tCHAV tCHCL tCHRL tAVCKNote 2 tDVCL tCHDV Notes 1. This indicates that there are four possible relationships between BUSCLK signal and other system bus interface signals. 2. This indicates the minimum setup time to the BUSCLK signal rising or falling edge. Remark The broken lines indicate high impedance. 52 Data Sheet U14691EJ1V0DS00 PD30121 (12) System bus parameter (IOCHRDY) (3/3) When WISAA (0:2) bits = 010, BSEL bit = 1 tBCLKH2 tBCLKL2 BUSCLK (output) ADD (19:25), ADD (0:8) (output) ADD (9:18) (output) tAVCL SHB# (output) tCLCKNote MEMR#/MEMW#, IOR#/IOW# (output) IOCHRDY (input) ZWS# (input) tAVSV1 MEMCS16#, IOCS16# (input) DATA (output) DATA (input) Invalid tDS Invalid tDH Invalid tCHSV tCLCH tCLR tRHCH tCHRL tCHAV tCHCL tAVCKNote tDVCL tCHDV Note This indicates the minimum setup time to the BUSCLK signal rising edge. Remark The broken lines indicate high impedance. Data Sheet U14691EJ1V0DS00 53 PD30121 (13) System bus parameter (ZWS#) (1/2) Parameter Address setup time (to BUSCLK) Address setup time (to command signal ) Command signal setup time (to BUSCLK) Command signal low-level width Notes 1, 2 Notes 1, 2 Note 1 Symbol tAVCK tAVCL tCLCK tCLCH Note 1 Condition MIN. 15 T x N - 29 15 T x N - 19 25 T x (N + 1) - 29 MAX. Unit ns ns ns ns ns ns Address hold time (from command signal ) Command signal recovery time Notes 1, 2 tCHAV tCHCL ZWS# delay time from command signal ZWS# hold time (from command signal ) Notes 1, 2 tCLZL tCHZH 0 0 25 2 x T x (N - 1) - 44 0 0 5 T x (N - 1) - 20 ns ns ns ns ns ns ns ns Note 1 Data output setup time (to command signal ) MEMCS16#/IOCS16# sampling start time Note 2 Note 1 tDVCL tCHDV tAVSV2 tCHSV tDS tDH Data output hold time (from command signal ) Note 1 MEMCS16#/IOCS16# hold time (from command Note 1 signal ) Data input setup time Data input hold time Notes 1. With the VR4121, the MEMW#, MEMR#, IOW#, and IOR# signals are called the command signals for the system bus interface. 2. The value of N is set by using the WISAA (0:2) bits of the BCUSPEEDREG register. The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and DTR#/CLKSEL0 pins). CLKSEL2 Signal 1 1 1 1 0 0 0 0 CLKSEL1 Signal 1 1 0 0 1 1 0 0 CLKSEL0 Signal 1 0 1 0 1 0 1 0 T (ns) RFU 35 33 30 33 30 33 38 WISAA2 Bit 0 0 0 0 1 1 Note Note WISAA1 Bit 0 0 1 1 0 0 Note Note WISAA0 Bit 0 1 0 1 0 1 Note Note N (TClock) 8 7 6 5 4 3 1 1 1 1 0 1 Remarks 1. Do not set CLKSEL (2:0) signal = 111. 2. Do not set CLKSEL (2:0) signal = 110, 101 with 131 MHz model. Note If the WISAA (0:2) bits are set to 100 or high, the AC characteristics of tCLCK and tAVCK are not guaranteed. 54 Data Sheet U14691EJ1V0DS00 PD30121 (13) System bus parameter (ZWS#) (2/2) When WISAA (0:2) bits = 101, BSEL bit = 0 BUSCLKNote 1 (output) BUSCLKNote 1 (output) BUSCLKNote 1 (output) BUSCLKNote 1 (output) ADD (19:25), ADD (0:8) (output) ADD (9:18) (output) tAVCL SHB# (output) MEMR#/MEMW#, IOR#/IOW# (output) IOCHRDY (input) ZWS# (input) tAVSV2 MEMCS16#, IOCS16# (input) tDVCL DATA (output) DATA (input) Invalid tDS Invalid tDH Invalid tCLCKNote 2 tCLCH tCHAV tCHCL tAVCKNote 2 tCLZL tCHZH tCHSV tCHDV Notes 1. This indicates that there are four possible relationships between BUSCLK signal and other system bus interface signals. 2. This indicates the minimum setup time to the BUSCLK signal rising or falling edge. Remark The broken lines indicate high impedance. Data Sheet U14691EJ1V0DS00 55 PD30121 (14) High-speed system bus parameter (IOCHRDY) (1/2) Parameter Address setup time (to command signal ) Command signal low-level width Notes 1, 2 Notes 1, 2 Symbol tAVCL tCLCH Note 1 Condition MIN. T x N - 29 T x (N + M) - 29 MAX. Unit ns ns ns ns ns Address hold time (from command signal ) Command signal recovery time IOCHRDY sampling start time Notes 1, 2 tCHAV tCHCL tCLR Notes 1, 2 25 T x (N + 1) - 29 0 TxM 0 -15 25 2 x T x N - 44 0 0 5 T x (N + M) + 29 Command signal delay time from IOCHRDY IOCHRDY hold time (from command signal ) Data output setup time (to command signal ) MEMCS16#/IOCS16# sampling start time Note 2 tRHCH tCHRL tDVCL tCHDV tAVSV1 tCHSV tDS tDH ns ns ns ns ns ns ns ns Note 1 Note 1 Data output hold time (from command signal ) Note 1 MEMCS16#/IOCS16# hold time (from command Note 1 signal ) Data input setup time Data input hold time Notes 1. With the VR4121, the MEMW# and MEMR# signals are called the command signals for the high-speed system bus interface. 2. The values of N and M are set by using the WLCD/M (0:2) bits of the BCUSPEEDREG register. The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and DTR#/CLKSEL0 pins). CLKSEL2 Signal 1 1 1 1 0 0 0 0 CLKSEL1 Signal 1 1 0 0 1 1 0 0 CLKSEL0 Signal 1 0 1 0 1 0 1 0 WLCD/M2 Bit 0 0 0 0 1 1 1 1 WLCD/M1 Bit 0 0 1 1 0 0 1 1 WLCD/M0 Bit 0 1 0 1 0 1 0 1 N (TClock) 8 7 6 5 4 3 2 1 M (TClock) 8 7 6 5 4 3 2 2 T (ns) RFU 35 33 30 33 30 33 38 Remarks 1. Do not set CLKSEL (2:0) signal = 111. 2. Do not set CLKSEL (2:0) signal = 110, 101 with 131 MHz model. 56 Data Sheet U14691EJ1V0DS00 PD30121 (14) High-speed system bus parameter (IOCHRDY) (2/2) When WISAA (2:0) bits = 111 ADD (19:25), ADD (0:8) (output) ADD (9:18) (output) SHB# (output) LCDCS# (output) tAVCL MEMR#/MEMW# (output) tCLR IOCHRDY (input) tRHCH tCHRL ZWS# (input) tAVSV1 MEMCS16#, IOCS16# (input) tDVCL DATA (output) Invalid tDS DATA (input) Invalid tDH Invalid tCHDV tCHSV tCLCH tCHCL tCHAV Remark The broken lines indicate high impedance. Data Sheet U14691EJ1V0DS00 57 PD30121 (15) High-speed system bus parameter (ZWS#) (1/2) Parameter Address setup time (to command signal ) Command signal low-level width Notes 1, 2 Notes 1, 2 Symbol tAVCL tCLCH Note 1 Condition MIN. T x N - 29 T x N - 19 25 T x (N + 1) - 29 MAX. Unit ns ns ns ns Address hold time (from command signal ) Command signal recovery time Notes 1, 2 tCHAV tCHCL ZWS# delay time from command signal Notes 1, 2 tCLZL tCHZH tDVCL tCHDV tAVSV2 tCHSV tDS tDH 0 -15 25 2 x T x (N - 1) - 44 0 0 5 T x (N - 1) - 20 ns ns ns ns ns ns ns ns ZWS# signal hold time (from command signal ) Data output setup time (to command signal ) MEMCS16#/IOCS16# sampling start time Note 2 Note 1 Note 1 Data output hold time (from command signal ) Note 1 MEMCS16#/IOCS16# hold time (from command Note 1 signal ) Data input setup time Data input hold time Notes 1. With the VR4121, the MEMW# and MEMR# signals are called the command signals for the high-speed system bus interface. 2. The value of N is set by using the WISAA (0:2) bits of the BCUSPEEDREG register. The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and DTR#/CLKSEL0 pins). CLKSEL2 Signal 1 1 1 1 0 0 0 0 CLKSEL1 Signal 1 1 0 0 1 1 0 0 CLKSEL0 Signal 1 0 1 0 1 0 1 0 N (TClock) 8 7 6 5 4 3 2 1 T (ns) RFU 35 33 30 33 30 33 38 WISAA2 Bit 0 0 0 0 1 1 1 1 WISAA1 Bit 0 0 1 1 0 0 1 1 WISAA0 Bit 0 1 0 1 0 1 0 1 Remarks 1. Do not set CLKSEL (2:0) signal = 111. 2. Do not set CLKSEL (2:0) signal = 110, 101 with 131 MHz model. 58 Data Sheet U14691EJ1V0DS00 PD30121 (15) High-speed system bus parameter (ZWS#) (2/2) When WISAA (0:2) bits = 111 ADD (19:25), ADD (0:8) (output) ADD (9:18) (output) SHB# (output) LCDCS# (output) tAVCL MEMR#/MEMW# (output) tCLCH tCHAV tCHCL IOCHRDY (input) tCLZL ZWS# (input) tAVSV2 MEMCS16#, IOCS16# (input) tDVCL DATA (output) DATA (input) Invalid tDS Invalid tDH Invalid tCHDV tCHZH tCHSV Remark The broken lines indicate high impedance. Data Sheet U14691EJ1V0DS00 59 PD30121 (16) LCD interface parameter (1/2) Parameter Address setup time (to command signal ) Command signal recovery time LCDRDY sampling start time Command signal delay time from LCDRDY LCDRDY hold time (from command signal ) Notes 1, 2 Note 1 Note 1 Note 1 Symbol tAS tAH tRY tCLR tRHCH tRYZ tDVCH tCHDV tDS tDH Note 1 Condition MIN. 15 0 30 0 TxN 0 T x (N + 2) 25 0 5 MAX. Unit ns ns ns ns Address hold time (from command signal ) T x (N + 2) + 29 ns ns ns ns ns ns Data output setup time (to command signal ) Data input setup time (to command signal ) Notes 1, 2 Data output hold time (from command signal ) Data input hold time (from command signal ) Note 1 Note 1 Note 1 Notes 1. With the VR4121, the RD# and WR# signals are called the command signals for the LCD interface. 2. The values of N is set by using the WLCD/M (0:1) bits of the BCUSPEEDREG register. The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and DTR#/CLKSEL0 pins). CLKSEL2 Signal 1 1 1 1 0 0 0 0 CLKSEL1 Signal 1 1 0 0 1 1 0 0 CLKSEL0 Signal 1 0 1 0 1 0 1 0 T (ns) RFU 35 33 30 33 30 33 38 WLCD/M1 Bit 0 0 1 1 WLCD/M0 Bit 0 1 0 1 N (TClock) 8 6 4 2 Remarks 1. Do not set CLKSEL (2:0) signal = 111. 2. Do not set CLKSEL (2:0) signal = 110, 101 with 131 MHz model. 60 Data Sheet U14691EJ1V0DS00 PD30121 (16) LCD interface parameter (2/2) ADD (19:20), ADD (0:8) (output) ADD (9:18) (output) SHB# (output) LCDCS# (output) tAS RD#/WR# (output) tCLR LCDRDY (input) tDVCH DATA (output) DATA (input) Invalid tDS tDH Invalid Invalid tCHDV tRHCH tAH tRY tRYZ Remark The broken lines indicate high impedance. Data Sheet U14691EJ1V0DS00 61 PD30121 (17) Bus hold parameter (1/2) Parameter HLDRQ# input pulse width Data floating delay time Data valid delay time HLDRQ# input pulse width Data floating delay time Data valid delay time MRAS (0:3)# precharge time UCAS#/LCAS# setup time Note Note Symbol tFHP tFOFF tFON tSHP tSOFF tSON tRPS tCSR Condition In Fullspeed/Standby mode In Fullspeed/Standby mode In Fullspeed/Standby mode In Suspend mode In Suspend mode In Suspend mode In Suspend mode In Suspend mode MIN. 5T 0 0 12T 0 0 110 5 MAX. Unit ns ns ns ns ns ns ns ns Note The value of T is set by using the CLKSEL (0:2) signals (TxD/CLKSEL2, RTS#/CLKSEL1, and DTR#/CLKSEL0 pins). CLKSEL2 Signal 1 1 1 1 0 0 0 0 CLKSEL1 Signal 1 1 0 0 1 1 0 0 CLKSEL0 Signal 1 0 1 0 1 0 1 0 T (ns) RFU 35 33 30 33 30 33 38 Remarks 1. Do not set CLKSEL (2:0) signal = 111. 2. Do not set CLKSEL (2:0) signal = 110, 101 with 131 MHz model. 62 Data Sheet U14691EJ1V0DS00 PD30121 (17) Bus hold parameter (2/2) (a) Bus hold in Fullspeed/Standby mode tFHP HLDRQ# (input) HLDACK# (output) Note 1 Note 2 BUSCLK (output) tFOFF tFON Notes 1. UUCAS#/MRAS3#, ULCAS#/MRAS2#, MRAS (0:1)#, UCAS#, LCAS# pins 2. SHB#, IOR#, IOW#, MEMR#, MEMW#, RD#, WR#, ADD (0:24), ADD25/SCLK, and DATA (0:15) pins, and DATA (16:31)/GPIO (16:31) pin in 32-bit mode Remark The broken lines indicate high impedance. (b) Bus hold in Suspend mode tSHP HLDRQ# (input) HLDACK# (output) Note 1 Note 2 Note 3 tRPS tSOFF tSON tRPS tCSR BUSCLK (output) H Notes 1. In 32-bit mode: MRAS (0:1)# pins In 16-bit mode: UUCAS#/MRAS3#, ULCAS#/MRAS2#, MRAS (0:1)# pins 2. In 32-bit mode: UUCAS#/MRAS3#, ULCAS#/MRAS2#, UCAS#, LCAS# pins In 16-bit mode: UCAS#, LCAS# pins 3. SHB#, IOR#, IOW#, MEMR#, MEMW#, RD#, WR#, ADD (0:24), ADD25/SCLK, and DATA (0:15) pins, and DATA (16:31)/GPIO (16:31) pins in 32-bit mode Remark The broken lines indicate high impedance. Data Sheet U14691EJ1V0DS00 63 PD30121 (18) Keyboard Interface parameter (1/2) Parameter KSCAN (0:11) high-level width Idle time (KSCAN (n+1) from KSCANn ) Key scan interval time Key input setup time (to KSCANn ) Key input hold time (from KSCANn ) Symbol tSCAN tKWAIT tKI tKS tKH Condition MIN. 30 (K + 2) - 1 30 (L + 1) - 1 30M - 1 30 (N + 1) - 1 0 MAX. 30.16 (K + 2) + 1 30.16 (L + 1) + 1 30.16M + 1 Unit s s s s s Notes 1. K: Sum of the values set to the T1CNT (0:4) bits and T2CNT (0:4) bits of the KIUWKS register 2. L: Value set to the T3CNT (0:4) bits of the KIUWKS register 3. M: Value set to KIUWKI register 4. N: Value set to the T1CNT (0:4) bits of the KIUWKS register 5. n = 0 to 11 (a) Keyboard scan parameter 1 tSCAN KSCANn (output) Hi-Z Hi-Z tKWAIT KSCAN (n + 1) (output) Hi-Z Remark n = 0 to 10 (b) Keyboard scan parameter 2 tKWAIT tKWAIT tKWAIT + tKI KSCAN0 Hi-Z (output) Hi-Z KSCAN1 (output) Hi-Z KSCAN2 (output) Hi-Z Hi-Z Hi-Z KSCAN11 (output) Hi-Z Hi-Z 64 Data Sheet U14691EJ1V0DS00 PD30121 (18) Keyboard Interface parameter (2/2) (c) Keyboard port parameter KSCANn (output) KPORT (0:7) (input) Hi-Z tKS tKH Hi-Z Remark n = 0 to 11 Data Sheet U14691EJ1V0DS00 65 PD30121 (19) Serial interface parameter (1/2) Parameter TxD output pulse width RxD input pulse width Note Note Symbol tTXD tRXD Note Condition MIN. N-1 (9/16) x N (3/16) x N - 1 1 MAX. N+1 (3/16) x N + 1 Unit s s s s IRDOUT# high-level output pulse width IRDIN input pulse width tIRDOUT tIRDIN Note N: Data transfer rate per bit, which is determined by the divisor of the baud-rate generator that is set with the SIUDLL and SIUDLM registers. Baud Rate (bps) 50 75 110 134.5 150 300 600 1,200 1,800 2,000 2,400 3,600 4,800 7,200 9,600 19,200 38,400 56,000 128,000 144,000 192,000 230,400 288,000 384,000 576,000 1,152,000 SIUDLM, SIUDLL Resister 23,040 15,360 10,473 8,565 7,680 3,840 1,920 920 640 573 480 320 240 160 120 60 30 21 9 8 6 5 4 3 2 1 N (s) 20,000 13,333 9,091 7,435 6,667 3,333 1,667 833 556 500 417 278 208 139 104 52.1 26.0 17.9 7.81 6.94 5.21 4.34 3.47 2.60 1.74 0.868 66 Data Sheet U14691EJ1V0DS00 PD30121 (19) Serial interface parameter (2/2) TxD (output) tTXD RxD (input) tRXD IRDOUT# (output) tIRDOUT IRDIN (input) tIRDIN Data Sheet U14691EJ1V0DS00 67 PD30121 (20) Debug serial interface parameter Parameter DDOUT output pulse width DDIN input pulse width Note Note Symbol tDDOUT tDDIN Condition MIN. N-1 (9/16) x N MAX. N+1 Unit s s Note N: Transfer rate of baud rate per bit set to the BPR0 bits of the BPRM0REG register. BPR0 (2:0) Bits 111 110 101 100 011 010 001 000 Baud Rate (bps) 115,200 57,600 38,400 19,200 9,600 4,800 2,400 1,200 N (s) 8.68 17.36 26.04 52.03 104.16 208.33 416.66 833.33 DDIN (input) tDDIN DDOUT (output) tDDOUT (21) HSP interface parameter Parameter SDO output delay time SDI setup time SDI hold time Note 2 Note 2 Note 1 Symbol tSDOD tSDIS tSDIH tFSIS tFSIH Condition MIN. MAX. 15 Unit ns ns ns ns ns 25 0 20 0 FS setup time FS hold time Note 2 Note 2 Notes 1. The reference clock of this parameter is the rising edge of HSPSCLK signal. 2. The reference clock of this parameter is the falling edge of HSPSCLK signal. 68 Data Sheet U14691EJ1V0DS00 PD30121 (22) SDRAM interface parameter Parameter SCLK clock cycle SCLK high-level width SCLK low-level width Data output delay time (from SCLK ) Address output delay time (from SCLK ) WR# output delay time (from SCLK ) Data input setup time Data input hold time Symbol tSCLK tSCLKH tSCLKL tDSM tDSA tDSW tSDS tSDH Note Note Condition MIN. 13.7 3.5 3.5 1.1 -5.8 1.1 6.2 2.9 10.7 17.6 24.5 MAX. Unit ns ns ns ns ns ns ns ns Note DATA (0:15) pins and DATA (16:31)/GPIO (16:31) pins in 32-bit mode tSCLKH SCLK (output) tDSM Note 1 tSCLKL tSCLK tDSA ADD (9:24), SCAS#, SRAS# (output) tDSW WR# (output) tSDS DATANote 2 (input) tSDH Notes 1. MRAS (0:1)#, ROMCS (2:3)#, UUCAS#/MRAS3#, ULCAS#/MRAS2#, UCAS#, LCAS#, CKE, and DATA (0:15) pins, and DATA (16:31)/GPIO (16:31) pins in 32-bit mode 2. DATA (0:15) pins, and DATA (16:31)/GPIO (16:31) pins in 32-bit mode Remark The broken lines indicate high impedance. Data Sheet U14691EJ1V0DS00 69 PD30121 A/D Converter Characteristics (131 MHz model: TA = -10 to +70C, VDD2 = 2.3 to 2.7 V, VDD3 = 3.0 to 3.45 V 168 MHz model: TA = -10 to +70C, VDD2 = 2.6 to 2.7 V, VDD3 = 3.0 to 3.45 V) Parameter Resolution Zero-scale error Full-scale error Notes 1, 2 Symbol Condition MIN. 10 TYP. MAX. Unit bit ZSE RSE Notes 1, 2 0 0 0 0 -0.3 4.0 5.0 3.0 3.0 AVDD + 0.3 LSB LSB LSB LSB V Notes 1, 2 Integral linearity error INL DNL VIAN Differential linearity error Analog input voltage Notes 1, 2 Notes 1, 3 Notes 1. Applied to TPX (0:1), TPY (0:1), ADIN (0:2), and AUDIOIN pins. 2. Quantization error is excluded. 3. AVDD is a voltage on the AVDD pin that is VDD dedicated to the A/D converter. D/A Converter Characteristics (131 MHz model: TA = -10 to +70C, VDD2 = 2.3 to 2.7 V, VDD3 = 3.0 to 3.45 V 168 MHz model: TA = -10 to +70C, VDD2 = 2.6 to 2.7 V, VDD3 = 3.0 to 3.45 V) Parameter Resolution Integral linearity error Notes 1, 2 Symbol Condition MIN. 10 TYP. MAX. Unit bit INL DNL 0 0 3.0 3.0 LSB LSB Differential linearity error Notes 1, 2 Notes 1. Applied to AUDIOOUT pin. 2. Quantization error is excluded. Load Coefficient (Delay Time per Load Capacitance) Parameter Symbol Condition Rating MIN. Load coefficient CLD MAX. 5 ns/20 pF Unit Caution Because NEC confirmed the characteristics by simulation at the design phase, screening on shipment is omitted. 70 Data Sheet U14691EJ1V0DS00 PD30121 3. PACKAGE DRAWING 224-PIN PLASTIC FBGA (16x16) A B W SB B 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 V U T R P NM L K J HG F E D C B A A CD Index mark Q W P SA J R S ITEM A B C D E F G H I J K L M P Q R W Y1 MILLIMETERS 16.000.10 15.4 15.4 16.000.10 1.20 0.8 (T.P.) 0.350.1 0.36 0.96 1.310.15 0.10 Y1 S H I K S L F E G M M SAB 0.50 +0.05 -0.10 0.08 C1.0 R0.3 25 0.20 0.20 S224S1-80-3C-2 Data Sheet U14691EJ1V0DS00 71 PD30121 4. RECOMMENDED SOLERING CONDITIONS The PD30121 should be soldered and mounted under the following recommended conditions. For details of recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 4-1. Surface Mounting Type Soldering Conditions PD30121F1-131-GA1: 224-pin plastic FBGA (16 x 16) PD30121F1-168-GA1: 224-pin plastic FBGA (16 x 16) Soldering Method Infrared reflow Soldering Conditions Recommended Condition Symbol IR30-103-2 Package peak temperature: 230C, Time: 30 seconds max. (at 210C or Note higher), Count: 2 times max., Exposure limit: 3 days (after that, prebake at 125C for 10 to 72 hours.) VPS Package peak temperature: 215C, Time: 25 to 40 seconds (at 200C or Note higher), Count: 2 times max. , Exposure limit: 3 days (after that, prebake at 125C for 10 to 72 hours.) VP15-103-2 Partial heating Pin temperature: 300C max., Time: 3 seconds max. (per pin row) Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). 72 Data Sheet U14691EJ1V0DS00 PD30121 [MEMO] Data Sheet U14691EJ1V0DS00 73 PD30121 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 74 Data Sheet U14691EJ1V0DS00 PD30121 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829 J99.1 Data Sheet U14691EJ1V0DS00 75 PD30121 Reference document Electrical Characteristics for Microcomputer (IEI-601) Note Note This document number is that of the Japanese version. The documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. VR4120, VR4121, and VR Series are trademarks of NEC Corporation. MIPS is a registered trademark of MIPS Technologies, Inc. in the United States. The technology used for the HSP (Modem Interface Unit) incorporated in this product is the intellectual porperty of the PC-TEL, Incorporated. The use of this interface in product development therefore requires the prior approval of PC-TEL, Incorporated. Exporting this product or equipment that includes this product may require a governmental license from the U.S.A. for some countries because this product utilizes technologies limited by the export control regulations of the U.S.A. * The information in this document is current as of June, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 |
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